Gated Twin-Bit (GTB) nonvolatile memory device and its operation

Seongjae Cho; Il Han Park; Jung Hoon Lee; Jang Gn Yun; Doo Hyun Kim; Gil Sung Lee; Hyungcheol Shin; Jong Duk Lee; Byung Gook Park

doi:10.1109/SNW.2008.5418396

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

Seongjae Cho, Il Han Park, Jung Hoon Lee, Jang Gn Yun, Doo Hyun Kim, Gil Sung Lee, Hyungcheol Shin, Jong Duk Lee, Byung Gook Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this study, a nonvolatile memory (NVM) device with a novel 3-dimensional structure is introduced. The device is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between pillars can be removed and additional gates called cut-off gates help the operation. In this sense, GTB NVM device is considered as the ultimate form of 3-D nonvolatile memory device based on double-gate structure. Also, the operation is validated by simulation works.

Original language	English
Title of host publication	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs	https://doi.org/10.1109/SNW.2008.5418396
State	Published - 2008
Event	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States Duration: 15 Jun 2008 → 16 Jun 2008

Publication series

Name	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Conference

Conference	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Country/Territory	United States
City	Honolulu, HI
Period	15/06/08 → 16/06/08

Access to Document

10.1109/SNW.2008.5418396

Cite this

@inproceedings{eebc432e3853409487468aac8cd89827,

title = "Gated Twin-Bit (GTB) nonvolatile memory device and its operation",

abstract = "In this study, a nonvolatile memory (NVM) device with a novel 3-dimensional structure is introduced. The device is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between pillars can be removed and additional gates called cut-off gates help the operation. In this sense, GTB NVM device is considered as the ultimate form of 3-D nonvolatile memory device based on double-gate structure. Also, the operation is validated by simulation works.",

author = "Seongjae Cho and Park, {Il Han} and Lee, {Jung Hoon} and Yun, {Jang Gn} and Kim, {Doo Hyun} and Lee, {Gil Sung} and Hyungcheol Shin and Lee, {Jong Duk} and Park, {Byung Gook}",

year = "2008",

doi = "10.1109/SNW.2008.5418396",

language = "English",

isbn = "9781424420711",

series = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

booktitle = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

note = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 ; Conference date: 15-06-2008 Through 16-06-2008",

}

Cho, S, Park, IH, Lee, JH, Yun, JG, Kim, DH, Lee, GS, Shin, H, Lee, JD & Park, BG 2008, Gated Twin-Bit (GTB) nonvolatile memory device and its operation. in IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008., 5418396, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, Honolulu, HI, United States, 15/06/08. https://doi.org/10.1109/SNW.2008.5418396

TY - GEN

T1 - Gated Twin-Bit (GTB) nonvolatile memory device and its operation

AU - Cho, Seongjae

AU - Park, Il Han

AU - Lee, Jung Hoon

AU - Yun, Jang Gn

AU - Kim, Doo Hyun

AU - Lee, Gil Sung

AU - Shin, Hyungcheol

AU - Lee, Jong Duk

AU - Park, Byung Gook

PY - 2008

Y1 - 2008

N2 - In this study, a nonvolatile memory (NVM) device with a novel 3-dimensional structure is introduced. The device is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between pillars can be removed and additional gates called cut-off gates help the operation. In this sense, GTB NVM device is considered as the ultimate form of 3-D nonvolatile memory device based on double-gate structure. Also, the operation is validated by simulation works.

AB - In this study, a nonvolatile memory (NVM) device with a novel 3-dimensional structure is introduced. The device is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between pillars can be removed and additional gates called cut-off gates help the operation. In this sense, GTB NVM device is considered as the ultimate form of 3-D nonvolatile memory device based on double-gate structure. Also, the operation is validated by simulation works.

UR - http://www.scopus.com/inward/record.url?scp=77949929955&partnerID=8YFLogxK

U2 - 10.1109/SNW.2008.5418396

DO - 10.1109/SNW.2008.5418396

M3 - Conference contribution

AN - SCOPUS:77949929955

SN - 9781424420711

T3 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

T2 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Y2 - 15 June 2008 through 16 June 2008

ER -

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

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