This paper presents a fixed-point error analysis for the unified systolic array implementation of 2-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse discrete cosine transform (IDCT). Closed form expressions for the mean and variance of fixed-point rounding-errors and truncation-errors are derived. Simulation results are provided to verify the analysis. Simulations designed to find the minimum word-length which satisfies IEEE requirements for the implementation of an 8×8 IDCT are also performed. Simulation results show that the proposed systolic array is more robust for the fixed-point error than other existing implementations for DCT/IDCT.
|Number of pages||10|
|State||Published - 1996|
|Event||Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors - Chicago, IL, USA|
Duration: 19 Aug 1996 → 21 Aug 1996
|Conference||Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures and Processors|
|City||Chicago, IL, USA|
|Period||19/08/96 → 21/08/96|