Fin-width dependence of BJT-based 1T-DRAM implemented on FinFET

Dong Il Moon; Sung Jin Choi; Jin Woo Han; Sungho Kim; Yang Kyu Choi

doi:10.1109/LED.2010.2052015

Fin-width dependence of BJT-based 1T-DRAM implemented on FinFET

Dong Il Moon, Sung Jin Choi, Jin Woo Han, Sungho Kim, Yang Kyu Choi

Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

15 Scopus citations

Abstract

This letter investigates fin-width dependence on single-transistor latch (STL) for bipolar-junction-transistor (BJT)-based 1T-DRAM through experiments. The minimum drain voltage (V_latch) for the activation of a parasitic lateral BJT in SOI FinFET was measured at various gate lengths (L_G's) and fin widths (W_fin's). The multiplication factor and current gain of the parasitic BJT in SOI MOSFET are introduced as determinant factors. The experimental results clearly show that the value of V_latch is reduced in a shorter L_G and wider W_fin device. It was found that the nonlocal effect retards the reduction of V_latch as FinFET scales down.

Original language	English
Article number	5512596
Pages (from-to)	909-911
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	31
Issue number	9
DOIs	https://doi.org/10.1109/LED.2010.2052015
State	Published - Sep 2010

Keywords

Bipolar-junction-transistor (BJT)-based 1T-DRAM
capacitorless 1T-DRAM
DRAM
embedded memory
FinFET
nonlocal effect
parasitic BJT
single-transistor latch (STL)
SOI MOSFET

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10.1109/LED.2010.2052015

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title = "Fin-width dependence of BJT-based 1T-DRAM implemented on FinFET",

abstract = "This letter investigates fin-width dependence on single-transistor latch (STL) for bipolar-junction-transistor (BJT)-based 1T-DRAM through experiments. The minimum drain voltage (Vlatch) for the activation of a parasitic lateral BJT in SOI FinFET was measured at various gate lengths (LG's) and fin widths (Wfin's). The multiplication factor and current gain of the parasitic BJT in SOI MOSFET are introduced as determinant factors. The experimental results clearly show that the value of Vlatch is reduced in a shorter LG and wider Wfin device. It was found that the nonlocal effect retards the reduction of Vlatch as FinFET scales down.",

keywords = "Bipolar-junction-transistor (BJT)-based 1T-DRAM, capacitorless 1T-DRAM, DRAM, embedded memory, FinFET, nonlocal effect, parasitic BJT, single-transistor latch (STL), SOI MOSFET",

author = "Moon, {Dong Il} and Choi, {Sung Jin} and Han, {Jin Woo} and Sungho Kim and Choi, {Yang Kyu}",

year = "2010",

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doi = "10.1109/LED.2010.2052015",

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AU - Moon, Dong Il

AU - Choi, Sung Jin

AU - Han, Jin Woo

AU - Kim, Sungho

AU - Choi, Yang Kyu

PY - 2010/9

Y1 - 2010/9

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AB - This letter investigates fin-width dependence on single-transistor latch (STL) for bipolar-junction-transistor (BJT)-based 1T-DRAM through experiments. The minimum drain voltage (Vlatch) for the activation of a parasitic lateral BJT in SOI FinFET was measured at various gate lengths (LG's) and fin widths (Wfin's). The multiplication factor and current gain of the parasitic BJT in SOI MOSFET are introduced as determinant factors. The experimental results clearly show that the value of Vlatch is reduced in a shorter LG and wider Wfin device. It was found that the nonlocal effect retards the reduction of Vlatch as FinFET scales down.

KW - Bipolar-junction-transistor (BJT)-based 1T-DRAM

KW - capacitorless 1T-DRAM

KW - DRAM

KW - embedded memory

KW - FinFET

KW - nonlocal effect

KW - parasitic BJT

KW - single-transistor latch (STL)

KW - SOI MOSFET

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Fin-width dependence of BJT-based 1T-DRAM implemented on FinFET

Abstract

Keywords

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