Feasibility of a Dual-Gate Graphene Transistor to Test Various Gate Dielectrics for Two-Dimensional Device Application

Nahee Park, Dongseok Suh, Haeyong Kang

Research output: Contribution to journalArticlepeer-review

Abstract

Graphene transistors with a dual-gate structure have been fabricated to study the effects of a functional dielectric substrate. From graphene’s conductance modulation by using dual-gate voltage control in which a polymethyl methacrylate (PMMA) layer is employed as a top-gate dielectric, we propose that the interaction between the graphene and the functional material working as a back-gate dielectric substrate can be understood. We evaluated two graphene devices, one having the standard structure of Si/SiO2/graphene/PMMA/top-gate and the other employing periodically poled lithium niobate (PPLN) with the structure of PPLN/graphene/PMMA/top-gate. The feasibility of this approach is discussed in terms of the effect of the alternating polarization domains on graphene’s charge transport.

Original languageEnglish
Pages (from-to)888-892
Number of pages5
JournalJournal of the Korean Physical Society
Volume77
Issue number10
DOIs
StatePublished - Nov 2020

Bibliographical note

Funding Information:
This work was supported by the Korea Electric Power Corporation (No. R18XA06-54), Republic of Korea, and by the National Research Foundation of Korea (No. NRF-2018R1A2B6004710), Republic of Korea.

Publisher Copyright:
© 2020, The Korean Physical Society.

Keywords

  • 2D materials
  • Dual-gate
  • Ferroelectric
  • Field-effect transistor
  • Graphene

Fingerprint

Dive into the research topics of 'Feasibility of a Dual-Gate Graphene Transistor to Test Various Gate Dielectrics for Two-Dimensional Device Application'. Together they form a unique fingerprint.

Cite this