Abstract
A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped n+ source and drain junctions, nearly intrinsic n- channel, 500-nm gate length (LG), and 50-nm poly-Si body thickness (Tbody). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2μA/μm and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.
Original language | English |
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Article number | 8649591 |
Pages (from-to) | 566-569 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 40 |
Issue number | 4 |
DOIs | |
State | Published - Apr 2019 |
Bibliographical note
Funding Information:Manuscript received February 10, 2019; revised February 18, 2019; accepted February 19, 2019. Date of publication February 22, 2019; date of current version April 2, 2019. This work was supported in part by the Ministry of Trade, Industry and Energy (MOTIE) with the Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor devices under Grant 10080513, and in part by the Ministry of Science and ICT (MSIT) of Korea for Mid-Career Researcher Program under Grant 2017R1A2B2011570. The review of this letter was arranged by Editor B. S. Doyle. (Jae Hwa Seo and Young Jun Yoon contributed equally to this work.) (Corresponding authors: Jong-Ho Lee; Seongjae Cho.) J. H. Seo and J.-H. Lee are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea (e-mail: jhl@snu.ac.kr).
Publisher Copyright:
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Keywords
- 1T DRAM
- embedded DRAM
- grain boundary
- poly-Si
- retention
- sensing margin