Fabrication and characterization of a thin-body Poly-Si 1T DRAM with charge-trap effect

Jae Hwa Seo, Young Jun Yoon, Eunseon Yu, Wookyung Sun, Hyungsoon Shin, In Man Kang, Jong Ho Lee, Seongjae Cho

Research output: Contribution to journalArticlepeer-review

29 Scopus citations


A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped n+ source and drain junctions, nearly intrinsic n- channel, 500-nm gate length (LG), and 50-nm poly-Si body thickness (Tbody). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2μA/μm and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.

Original languageEnglish
Article number8649591
Pages (from-to)566-569
Number of pages4
JournalIEEE Electron Device Letters
Issue number4
StatePublished - Apr 2019

Bibliographical note

Publisher Copyright:
© 1980-2012 IEEE.


  • 1T DRAM
  • embedded DRAM
  • grain boundary
  • poly-Si
  • retention
  • sensing margin


Dive into the research topics of 'Fabrication and characterization of a thin-body Poly-Si 1T DRAM with charge-trap effect'. Together they form a unique fingerprint.

Cite this