Fabrication and characterization of a thin-body Poly-Si 1T DRAM with charge-trap effect

Jae Hwa Seo; Young Jun Yoon; Eunseon Yu; Wookyung Sun; Hyungsoon Shin; In Man Kang; Jong Ho Lee; Seongjae Cho

doi:10.1109/LED.2019.2901003

Fabrication and characterization of a thin-body Poly-Si 1T DRAM with charge-trap effect

Jae Hwa Seo, Young Jun Yoon, Eunseon Yu, Wookyung Sun, Hyungsoon Shin, In Man Kang, Jong Ho Lee, Seongjae Cho

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

27 Scopus citations

Abstract

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped n⁺ source and drain junctions, nearly intrinsic n^- channel, 500-nm gate length (L_G), and 50-nm poly-Si body thickness (T_body). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2μA/μm and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.

Original language	English
Article number	8649591
Pages (from-to)	566-569
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	4
DOIs	https://doi.org/10.1109/LED.2019.2901003
State	Published - Apr 2019

Bibliographical note

Funding Information:
Manuscript received February 10, 2019; revised February 18, 2019; accepted February 19, 2019. Date of publication February 22, 2019; date of current version April 2, 2019. This work was supported in part by the Ministry of Trade, Industry and Energy (MOTIE) with the Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor devices under Grant 10080513, and in part by the Ministry of Science and ICT (MSIT) of Korea for Mid-Career Researcher Program under Grant 2017R1A2B2011570. The review of this letter was arranged by Editor B. S. Doyle. (Jae Hwa Seo and Young Jun Yoon contributed equally to this work.) (Corresponding authors: Jong-Ho Lee; Seongjae Cho.) J. H. Seo and J.-H. Lee are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea (e-mail: jhl@snu.ac.kr).

Publisher Copyright:
© 1980-2012 IEEE.

Keywords

1T DRAM
embedded DRAM
grain boundary
poly-Si
retention
sensing margin

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10.1109/LED.2019.2901003

Cite this

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title = "Fabrication and characterization of a thin-body Poly-Si 1T DRAM with charge-trap effect",

abstract = "A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped n+ source and drain junctions, nearly intrinsic n- channel, 500-nm gate length (LG), and 50-nm poly-Si body thickness (Tbody). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2μA/μm and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.",

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author = "Seo, {Jae Hwa} and Yoon, {Young Jun} and Eunseon Yu and Wookyung Sun and Hyungsoon Shin and Kang, {In Man} and Lee, {Jong Ho} and Seongjae Cho",

note = "Funding Information: Manuscript received February 10, 2019; revised February 18, 2019; accepted February 19, 2019. Date of publication February 22, 2019; date of current version April 2, 2019. This work was supported in part by the Ministry of Trade, Industry and Energy (MOTIE) with the Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor devices under Grant 10080513, and in part by the Ministry of Science and ICT (MSIT) of Korea for Mid-Career Researcher Program under Grant 2017R1A2B2011570. The review of this letter was arranged by Editor B. S. Doyle. (Jae Hwa Seo and Young Jun Yoon contributed equally to this work.) (Corresponding authors: Jong-Ho Lee; Seongjae Cho.) J. H. Seo and J.-H. Lee are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea (e-mail: jhl@snu.ac.kr). Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

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Fabrication and characterization of a thin-body Poly-Si 1T DRAM with charge-trap effect

Abstract

Bibliographical note

Keywords

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