Establishing read operation bias schemes for 3-d pillar structure flash memory devices to overcome paired cell interference (pci)

Efforts have been devoted to maximizing memory array densities. However, as the devices are sealed down in dimension and get ring closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are pro posed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as therepresentative, and investigate the paired cell interference (PCI) which in evitably occurs in the read operation for 3-D memory devices in this fea ture. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.