TY - JOUR
T1 - Energy-Efficient Design of Processing Element for Convolutional Neural Network
AU - Choi, Yeongjae
AU - Bae, Dongmyung
AU - Sim, Jaehyeong
AU - Choi, Seungkyu
AU - Kim, Minhye
AU - Kim, Lee Sup
N1 - Funding Information:
Manuscript received December 23, 2016; revised March 16, 2017; accepted April 1, 2017. Date of publication April 6, 2017; date of current version November 1, 2017. This work was supported by the National Research Foundation of Korea through the Korea Government (MSIP) under Grants NRF-2014R1A2A1A05004316 and 2010-0028680. This brief was recommended by Associate Editor C.-T. Cheng. (Corresponding author: Lee-Sup Kim.) The authors are with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, South Korea (e-mail: yjchoi@vlsi2.kaist.ac.kr; baedm12@vlsi2.kaist.ac.kr; jhsim@mvlsi.kaist.ac.kr; skchoi@vlsi2.kaist.ac.kr; mhkim@mvlsi.kaist.ac.kr; leesup@kaist.ac.kr).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2017/11
Y1 - 2017/11
N2 - Convolutional neural network (CNN) is the most prominent algorithm for its wide usage and good performance. Despite the fact that the processing element (PE) plays an important role in CNN processing, there has been no study focusing on PE design optimized for state-of-the-art CNN algorithms. In this brief, we propose an optimal PE implementation including a data representation scheme, circuit block configurations, and control signals for energy-efficient CNN. To validate the excellence of this brief, we compared our proposed design with several previous methods, and fabricated a silicon chip. The software simulation results demonstrated that we can reduce 54% of data bit lengths with negligible accuracy loss. Our optimization on PE achieves to save computing power up to 47%, and an accelerator exploiting our method shows superior results in terms of power, area, and external DRAM access.
AB - Convolutional neural network (CNN) is the most prominent algorithm for its wide usage and good performance. Despite the fact that the processing element (PE) plays an important role in CNN processing, there has been no study focusing on PE design optimized for state-of-the-art CNN algorithms. In this brief, we propose an optimal PE implementation including a data representation scheme, circuit block configurations, and control signals for energy-efficient CNN. To validate the excellence of this brief, we compared our proposed design with several previous methods, and fabricated a silicon chip. The software simulation results demonstrated that we can reduce 54% of data bit lengths with negligible accuracy loss. Our optimization on PE achieves to save computing power up to 47%, and an accelerator exploiting our method shows superior results in terms of power, area, and external DRAM access.
KW - convolutional neural network
KW - neural network processor
KW - Neuromorphic computing
KW - processing element
UR - http://www.scopus.com/inward/record.url?scp=85034251947&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2017.2691771
DO - 10.1109/TCSII.2017.2691771
M3 - Article
AN - SCOPUS:85034251947
SN - 1549-7747
VL - 64
SP - 1332
EP - 1336
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 11
M1 - 7893765
ER -