Abstract
In this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of the trapped charges should be beneficial in setting up an accurate compact model of CTF memory cell, where the charge centroid becomes a very practical means by which a rather large number of trapped electrons can be dealt in the more mathematical manner as a whole electron cloud. The relation between charge centroid and program voltage (VPGM) depending on nitride layer properties is analytically studied.
Original language | English |
---|---|
Title of host publication | 2017 Silicon Nanoelectronics Workshop, SNW 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 79-80 |
Number of pages | 2 |
ISBN (Electronic) | 9784863486478 |
DOIs | |
State | Published - 29 Dec 2017 |
Event | 22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan Duration: 4 Jun 2017 → 5 Jun 2017 |
Publication series
Name | 2017 Silicon Nanoelectronics Workshop, SNW 2017 |
---|---|
Volume | 2017-January |
Conference
Conference | 22nd Silicon Nanoelectronics Workshop, SNW 2017 |
---|---|
Country/Territory | Japan |
City | Kyoto |
Period | 4/06/17 → 5/06/17 |
Bibliographical note
Funding Information:This work was supported by Sarnsung Electronics Corp. and by the Brain Korea 21 Plus Program.
Publisher Copyright:
© 2017 JSAP.