Abstract
In this work, the effects of misalignment between gate and channel edges on performances of an ultra-thin vertical-pillar MOSFET are investigated by a series of device simulations. The operation characteristics of the device as a function of degree of misalignment that might frequently exist between the gate and channel edges, in the actual device fabrication, have been quantitatively analyzed. In case of gate-drain overlap, there is little change in current characteristics but significant decrease in Ion and increase in Ioff were observed, when an excessive underlap was established, accompanying non-ideal effects including subthreshold swing (S) degradation and drain-induced barrier lowering (DIBL). Based on the results, the process margin can be figured.
Original language | English |
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Title of host publication | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9798350371888 |
DOIs | |
State | Published - 2024 |
Event | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 - Taipei, Taiwan, Province of China Duration: 28 Jan 2024 → 31 Jan 2024 |
Publication series
Name | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
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Conference
Conference | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
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Country/Territory | Taiwan, Province of China |
City | Taipei |
Period | 28/01/24 → 31/01/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- gate misalignment
- non-ideal MOSFET operations
- process margin
- Ultra-thin body
- vertical-pillar MOSFET