Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET

Soomin Kim, Seongjae Cho

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, the effects of misalignment between gate and channel edges on performances of an ultra-thin vertical-pillar MOSFET are investigated by a series of device simulations. The operation characteristics of the device as a function of degree of misalignment that might frequently exist between the gate and channel edges, in the actual device fabrication, have been quantitatively analyzed. In case of gate-drain overlap, there is little change in current characteristics but significant decrease in Ion and increase in Ioff were observed, when an excessive underlap was established, accompanying non-ideal effects including subthreshold swing (S) degradation and drain-induced barrier lowering (DIBL). Based on the results, the process margin can be figured.

Original languageEnglish
Title of host publication2024 International Conference on Electronics, Information, and Communication, ICEIC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350371888
DOIs
StatePublished - 2024
Event2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 - Taipei, Taiwan, Province of China
Duration: 28 Jan 202431 Jan 2024

Publication series

Name2024 International Conference on Electronics, Information, and Communication, ICEIC 2024

Conference

Conference2024 International Conference on Electronics, Information, and Communication, ICEIC 2024
Country/TerritoryTaiwan, Province of China
CityTaipei
Period28/01/2431/01/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

  • gate misalignment
  • non-ideal MOSFET operations
  • process margin
  • Ultra-thin body
  • vertical-pillar MOSFET

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