Effects of gate/blocking oxide energy barrier on memory characteristics in charge trap flash memory cells

A charge trap flash (CTF) memory cell consists of oxide-nitride-oxide multilayer dielectrics and the electron/hole trapping within the silicon nitride layer is the main charge storage mechanism for program/erase operation. However, CTF memory cells have some technical issues, such as the electron back-tunneling phenomenon which causes the non-fully erased state and makes its memory window narrow and memory speed slow during erase operation. In this paper, we focus on the effects of the blocking oxide energy barrier from the control gate on the memory characteristics in CTF memory cells. Our experimental results show that a relatively high gate/blocking oxide energy barrier leads to a reduced non-fully erased state problem but a smaller program threshold voltage shift; conversely, a relatively low gate/blocking oxide energy barrier leads to a larger program threshold voltage shift but a significant non-fully erased state problem. All of these results will contribute to understand the trade-offs between the gate/blocking oxide energy barrier and memory window for optimizing CTF memory cell performance.