Abstract
This study introduces a partially reconfigurable system-on-chip (SoC) platform leveraging dynamic resource management facilitated by a dynamic reconfigurable control processor (DRCP). By addressing the inherent reconfiguration time overheads of reconfigurable SoCs, the study demonstrates performance improvements through a runtime resource management strategy. The introduced management scheme effectively reduces the frequency of reconfigurations, thus lessening the associated overheads and increasing the operational efficiency of the SoC platform, which is designed to support on-chip multi-tenancy. Utilizing DRCP for dedicated resource management, the proposed SoC platform exhibited substantial reductions in reconfiguration times. When the partially reconfigurable SoC platform employed four partial regions (PRs), the reconfiguration counts decreased by 37.6%. Furthermore, upon extending the PRs to eight, there was a notable reduction in reconfiguration counts, achieving a decrease of 47.0%.
Original language | English |
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Title of host publication | ISCAS 2024 - IEEE International Symposium on Circuits and Systems |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9798350330991 |
DOIs | |
State | Published - 2024 |
Event | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore Duration: 19 May 2024 → 22 May 2024 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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ISSN (Print) | 0271-4310 |
Conference
Conference | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 |
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Country/Territory | Singapore |
City | Singapore |
Period | 19/05/24 → 22/05/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Dynamic partial reconfiguration
- Dynamic resource management
- FPGA
- Multi-tenancy
- Reconfigurable SoC