Double-Gate Junctionless 1T DRAM with Physical Barriers for Retention Improvement

Md Hasan Raza Ansari, Nupur Navlakha, Jae Yoon Lee, Seongjae Cho

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27 Scopus citations

Abstract

In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time ( {T}_{\text {ret}} ) with larger physical barrier thickness ( {T}_{\text {oxPB}} ) and wider barrier offset length ( {L}_{\text {BO}} ) due to a reduction in band-to-band tunneling (BTBT) (during hold '0') and recombination (during hold '1'). Maximum retention times of 2.5 s and 33 ms have been achieved for channel doping of 1019 cm-3 at 27 °C and 85 °C, respectively, with gate length ( {L}_{g} ) of 100 nm at small drain bias ( {V}_{\text {DS}} ) of 1 V during write '1.' Results demonstrate a better gate length scalability and a retention time of 4 ms at {L}_{g} of 15 nm with thinner Si channel thickness under the gate ( {T}_{\text {Si}} ) and thicker {T}_{\text {oxPB}}. In addition, the effect of temperature on retention time has been analyzed. With optimized {T}_{\text {oxPB}} at {L}_{g} = {100} nm, the retention time decreases due to thermal generation and recombination from 2.5 s at 27 °C to 3 ms at 125 °C.

Original languageEnglish
Article number9039616
Pages (from-to)1471-1479
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume67
Issue number4
DOIs
StatePublished - Apr 2020

Bibliographical note

Funding Information:
Manuscript received February 18, 2020; accepted February 20, 2020. Date of publication March 17, 2020; date of current version March 24, 2020. This work was supported by the Ministry of Trade, Industry and Energy (MOTIE) and by the Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices under Grant 10080513. The review of this article was arranged by Editor P.-Y. Du. (Corresponding author: Seongjae Cho.) Md. Hasan Raza Ansari, Jae Yoon Lee, and Seongjae Cho are with the Department of Electronic Engineering, College of IT Convergence Engineering, Gachon University, Seongnam-si 13120, South Korea (e-mail: [email protected]).

Publisher Copyright:
© 1963-2012 IEEE.

Keywords

  • Double-gate (DG) junctionless (JL) transistor
  • One-transistor dynamic random-access memory (1T DRAM)
  • Physical barrier
  • Retention time
  • Temperature effect

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