Double-binary circular turbo decoding based on border metric encoding

Ji Hoon Kim; In Cheol Park

doi:10.1109/TCSII.2007.907803

Double-binary circular turbo decoding based on border metric encoding

Ji Hoon Kim, In Cheol Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

33 Scopus citations

Abstract

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-μm CMOS process, which can support 24.26 Mbps at 200 MHz.

Original language	English
Pages (from-to)	79-83
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	55
Issue number	1
DOIs	https://doi.org/10.1109/TCSII.2007.907803
State	Published - 2008

Keywords

Low power design
Maximum a posteriori (MAP) algorithm
Nonbinary turbo codes
Turbo decoding

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10.1109/TCSII.2007.907803

Cite this

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title = "Double-binary circular turbo decoding based on border metric encoding",

abstract = "This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-μm CMOS process, which can support 24.26 Mbps at 200 MHz.",

keywords = "Low power design, Maximum a posteriori (MAP) algorithm, Nonbinary turbo codes, Turbo decoding",

author = "Kim, {Ji Hoon} and Park, {In Cheol}",

note = "Funding Information: Manuscript received October 27, 2006; revised February 14, 2007 and June 18, 2007. This work was supported by the Institute of Information Technology Assessment through the ITRC and by IC Design Education Center (IDEC). This paper was recommended by Associate Editor M. Maggio.",

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PY - 2008

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N2 - This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-μm CMOS process, which can support 24.26 Mbps at 200 MHz.

AB - This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-μm CMOS process, which can support 24.26 Mbps at 200 MHz.

KW - Low power design

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Double-binary circular turbo decoding based on border metric encoding

Abstract

Keywords

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