Die-to-die Inspection of Semiconductor Wafer using Bayesian Twin Network

Eunjeong Choi, Jeongtae Kim

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


In this paper, we propose a deep learning-based die-to-die wafer inspection system, which is composed of an encoder-decoder-based twin network (Siamese network). In contrast to other deep learning-based wafer inspection methods, the proposed method takes golden and test die images as input and compares them to detect different areas as defects. In addition, we apply Bayesian learning to improve the performance of the proposed twin network. We verified the performance of the proposed method through experiments using patterned wafer images, which confirmed that the performance could be improved by applying Bayesian learning.

Original languageEnglish
Pages (from-to)382-389
Number of pages8
JournalIEIE Transactions on Smart Processing and Computing
Issue number5
StatePublished - 2021

Bibliographical note

Funding Information:
The authors are grateful to ATI Co., Ltd in Incheon, Korea for providing us the patterned wafer data. This work was supported by the grant from the ATI company and by the Ewha Womans University scholarship of 2019.

Publisher Copyright:
Copyrights © 2021 The Institute of Electronics and Information Engineers


  • Bayesian learning
  • Die-to-die inspection
  • Machine learning
  • Machine vision
  • Siamese network
  • Twin network
  • Wafer inspection


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