Die-to-die Inspection of Semiconductor Wafer using Bayesian Twin Network

Eunjeong Choi; Jeongtae Kim

doi:10.5573/IEIESPC.2021.10.5.382

Die-to-die Inspection of Semiconductor Wafer using Bayesian Twin Network

Eunjeong Choi, Jeongtae Kim

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

In this paper, we propose a deep learning-based die-to-die wafer inspection system, which is composed of an encoder-decoder-based twin network (Siamese network). In contrast to other deep learning-based wafer inspection methods, the proposed method takes golden and test die images as input and compares them to detect different areas as defects. In addition, we apply Bayesian learning to improve the performance of the proposed twin network. We verified the performance of the proposed method through experiments using patterned wafer images, which confirmed that the performance could be improved by applying Bayesian learning.

Original language	English
Pages (from-to)	382-389
Number of pages	8
Journal	IEIE Transactions on Smart Processing and Computing
Volume	10
Issue number	5
DOIs	https://doi.org/10.5573/IEIESPC.2021.10.5.382
State	Published - 2021

Bibliographical note

Funding Information:
The authors are grateful to ATI Co., Ltd in Incheon, Korea for providing us the patterned wafer data. This work was supported by the grant from the ATI company and by the Ewha Womans University scholarship of 2019.

Publisher Copyright:
Copyrights © 2021 The Institute of Electronics and Information Engineers

Keywords

Bayesian learning
Die-to-die inspection
Machine learning
Machine vision
Siamese network
Twin network
Wafer inspection

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10.5573/IEIESPC.2021.10.5.382

Cite this

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title = "Die-to-die Inspection of Semiconductor Wafer using Bayesian Twin Network",

abstract = "In this paper, we propose a deep learning-based die-to-die wafer inspection system, which is composed of an encoder-decoder-based twin network (Siamese network). In contrast to other deep learning-based wafer inspection methods, the proposed method takes golden and test die images as input and compares them to detect different areas as defects. In addition, we apply Bayesian learning to improve the performance of the proposed twin network. We verified the performance of the proposed method through experiments using patterned wafer images, which confirmed that the performance could be improved by applying Bayesian learning.",

keywords = "Bayesian learning, Die-to-die inspection, Machine learning, Machine vision, Siamese network, Twin network, Wafer inspection",

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AB - In this paper, we propose a deep learning-based die-to-die wafer inspection system, which is composed of an encoder-decoder-based twin network (Siamese network). In contrast to other deep learning-based wafer inspection methods, the proposed method takes golden and test die images as input and compares them to detect different areas as defects. In addition, we apply Bayesian learning to improve the performance of the proposed twin network. We verified the performance of the proposed method through experiments using patterned wafer images, which confirmed that the performance could be improved by applying Bayesian learning.

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Die-to-die Inspection of Semiconductor Wafer using Bayesian Twin Network

Abstract

Bibliographical note

Keywords

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