Device and circuit codesign strategy for application to low-noise amplifier based on silicon nanowire metal-oxide-semiconductor field effect transistors

In this study, a full-range approach from device level to circuit level design is performed for RF application of silicon nanowire (SNW) metal-oxide-semiconductor field effect transistors (MOSFETs). Both DC and AC analyses have been conducted to confirm the advantages of an SNW MOSFET over the conventional planar (CPL) MOSFET device having dimensional equivalence. Besides the intrinsic characteristic parameters, the extrinsic resistance and capacitance caused by wiring components are extracted from each device. On the basis of these intrinsic and extrinsic parameters, a multi-fingered 5.8GHz low-noise amplifier (LNA) design adopting SNW MOSFETs has been achieved, which shows an improved gain of 17.5 dB and a noise figure of 3.1 dB over a CPL MOSFET LNA.