Design optimization of InAs-based Gate-All-Around (GAA) arch-shaped Tunneling Field-Effect Transistor (TFET)

Jae Hwa Seo, Young Jun Yoon, Young Woo Jo, Dong Hyeok Son, Seongjae Cho, Hyuck In Kwon, Jung Hee Lee, In Man Kang

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

In this work, an InAs-based gate-all-around (GAA) arch-shaped tunneling field-effect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. To progress the DC/RF characteristics of GAA arch-shaped TFET, InAs, a highly attractive III-V compound material, is adopted as a channel material. Owing to the GAA arch-shaped structure of TFET, the tunneling region under the gate area is extended, and the on-state current (Ion) and subthreshold-swing (S) are improved. However, it has some performance limitations that are related to the height of the source region (Hsource) and the epitaxially grown thickness of the channel (tepi). Thus, we performed a design optimization of the InAs-based GAA arch-shaped TFET with the variables Hsource and tepi. After the optimization process, RF characteristics such as gate capacitance, transconductance (gm), cutoff frequency (fT), and maximum oscillation frequency (fmax) were extracted and analyzed by small-signal RF modeling. Finally, the designed InAs-based GAA arch-shaped TFET demonstrated an Ion of 10.6 mA/μm, S of 6.5 mV/dec, fT of 2.3 THz, and fmax of 20 THz.

Original languageEnglish
Pages (from-to)10199-10203
Number of pages5
JournalJournal of Nanoscience and Nanotechnology
Volume16
Issue number10
DOIs
StatePublished - Oct 2016

Bibliographical note

Publisher Copyright:
Copyright © 2016 American Scientific Publishers All rights reserved.

Keywords

  • Arch shape
  • GAA
  • III-V compound semiconductor
  • InAs
  • TCAD
  • TFET

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