Design of TETRA 2 turbo decoder with minimum memory hardware interleaver

Ji Hoon Kim

doi:10.1109/ISCAS.2012.6271610

Design of TETRA 2 turbo decoder with minimum memory hardware interleaver

Ji Hoon Kim

Electronic and Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

Terrestrial Trunked Radio (TETRA) is a digital trunked mobile radio standard developed by the European Telecommunications Standards Institute (ETSI). Especially, TETRA 2 supports different channel bandwidths and modulation techniques, and turbo code has been adopted as a channel code with powerful error correcting capability. In this paper, to lower the implementation cost of Takeshita-Costello interleaver adopted in TETRA 2, we present the simple interleaved address generation scheme which requires minimum memory size compared to the conventional memory-based interleaver. Also, overall TETRA 2 turbo decoder architecture including the proposed interleaver is described with its implementation results

Original language	English
Pages	1779-1782
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271610
State	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

Access to Document

10.1109/ISCAS.2012.6271610

Cite this

@conference{02f613cf7eee432fa212ee5121614aef,

title = "Design of TETRA 2 turbo decoder with minimum memory hardware interleaver",

abstract = "Terrestrial Trunked Radio (TETRA) is a digital trunked mobile radio standard developed by the European Telecommunications Standards Institute (ETSI). Especially, TETRA 2 supports different channel bandwidths and modulation techniques, and turbo code has been adopted as a channel code with powerful error correcting capability. In this paper, to lower the implementation cost of Takeshita-Costello interleaver adopted in TETRA 2, we present the simple interleaved address generation scheme which requires minimum memory size compared to the conventional memory-based interleaver. Also, overall TETRA 2 turbo decoder architecture including the proposed interleaver is described with its implementation results",

author = "Kim, {Ji Hoon}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271610",

language = "English",

pages = "1779--1782",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - Design of TETRA 2 turbo decoder with minimum memory hardware interleaver

AU - Kim, Ji Hoon

PY - 2012

Y1 - 2012

N2 - Terrestrial Trunked Radio (TETRA) is a digital trunked mobile radio standard developed by the European Telecommunications Standards Institute (ETSI). Especially, TETRA 2 supports different channel bandwidths and modulation techniques, and turbo code has been adopted as a channel code with powerful error correcting capability. In this paper, to lower the implementation cost of Takeshita-Costello interleaver adopted in TETRA 2, we present the simple interleaved address generation scheme which requires minimum memory size compared to the conventional memory-based interleaver. Also, overall TETRA 2 turbo decoder architecture including the proposed interleaver is described with its implementation results

AB - Terrestrial Trunked Radio (TETRA) is a digital trunked mobile radio standard developed by the European Telecommunications Standards Institute (ETSI). Especially, TETRA 2 supports different channel bandwidths and modulation techniques, and turbo code has been adopted as a channel code with powerful error correcting capability. In this paper, to lower the implementation cost of Takeshita-Costello interleaver adopted in TETRA 2, we present the simple interleaved address generation scheme which requires minimum memory size compared to the conventional memory-based interleaver. Also, overall TETRA 2 turbo decoder architecture including the proposed interleaver is described with its implementation results

UR - http://www.scopus.com/inward/record.url?scp=84866601850&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271610

DO - 10.1109/ISCAS.2012.6271610

M3 - Paper

AN - SCOPUS:84866601850

SP - 1779

EP - 1782

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

Design of TETRA 2 turbo decoder with minimum memory hardware interleaver

Abstract

Conference

Access to Document

Fingerprint

Cite this