Design of Poly-Si Junctionless Fin-Channel FET with Quantum-Mechanical Drift-Diffusion Models for Sub-10-nm Technology Nodes

Junsoo Lee, Youngmin Kim, Seongjae Cho

Research output: Contribution to journalArticlepeer-review

30 Scopus citations

Abstract

In this paper, a junctionless FinFET (JLFinFET) having polycrystalline-silicon (poly-Si) channel has been optimally designed and characterized by stringent device simulation aiming 10-nm-and-beyond Si technology node. Replacing the silicon-on-insulator platform employed for realizing the JLFETs in most cases by bulk Si substrate featuring deposited oxide and poly-Si channel would warrant highly cost-effective process integration. Here, the high- κ metal-gate technology is also adopted to enhance the gate controllability, prevent the gate leakage current, and obtain appropriate gate work function. It is demonstrated from the device simulation results with higher accuracy and credibility by multiple models, particularly including the quantum-mechanical models in drift and diffusion conductions that the poly-Si JL FinFET has the strong potential for the 10-nm-and-beyond Si CMOS technology with little performance degradation in comparison with the JL FinFET with crystalline Si channel.

Original languageEnglish
Article number7605508
Pages (from-to)4610-4616
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume63
Issue number12
DOIs
StatePublished - Dec 2016

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.

Keywords

  • Cost-effective process integration
  • FinFET
  • high- κ metal gate technology
  • junctionless field-effect transistor (JLFET)
  • polycrystalline-silicon (poly-Si) channel
  • quantum-mechanical drift-diffusion models
  • sub-10-nm Si CMOS technology

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