Design of high-performance 32-bit embedded processor

Kim Ji-Hoon, You Duk-Hyun, Kwon Ki-Seok, Bae Eun-Joo, Son WonHee, Park In-Cheol

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


This paper describes the implementation of highperformance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS rocess and the real-time edge detection system is designed with Altera FPGA for evaluation system.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
StatePublished - 2008
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 24 Nov 200825 Nov 2008

Publication series

Name2008 International SoC Design Conference, ISOCC 2008


Conference2008 International SoC Design Conference, ISOCC 2008
Country/TerritoryKorea, Republic of


  • Embedded processor
  • Soft-core
  • System on chip(SoC)


Dive into the research topics of 'Design of high-performance 32-bit embedded processor'. Together they form a unique fingerprint.

Cite this