@inproceedings{c3a83151c7a144b09a93cdb988d16dbe,
title = "Design of high-performance 32-bit embedded processor",
abstract = "This paper describes the implementation of highperformance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS rocess and the real-time edge detection system is designed with Altera FPGA for evaluation system.",
keywords = "Embedded processor, Soft-core, System on chip(SoC)",
author = "Kim Ji-Hoon and You Duk-Hyun and Kwon Ki-Seok and Bae Eun-Joo and Son WonHee and Park In-Cheol",
year = "2008",
doi = "10.1109/SOCDC.2008.4815746",
language = "English",
isbn = "9781424425990",
series = "2008 International SoC Design Conference, ISOCC 2008",
pages = "III54--III55",
booktitle = "2008 International SoC Design Conference, ISOCC 2008",
note = "null ; Conference date: 24-11-2008 Through 25-11-2008",
}