Design of high-performance 32-bit embedded processor

Kim Ji-Hoon; You Duk-Hyun; Kwon Ki-Seok; Bae Eun-Joo; Son WonHee; Park In-Cheol

doi:10.1109/SOCDC.2008.4815746

Design of high-performance 32-bit embedded processor

Kim Ji-Hoon, You Duk-Hyun, Kwon Ki-Seok, Bae Eun-Joo, Son WonHee, Park In-Cheol

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper describes the implementation of highperformance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS rocess and the real-time edge detection system is designed with Altera FPGA for evaluation system.

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Pages	III54-III55
DOIs	https://doi.org/10.1109/SOCDC.2008.4815746
State	Published - 2008
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 24 Nov 2008 → 25 Nov 2008

Publication series

Name	2008 International SoC Design Conference, ISOCC 2008
Volume	3

Conference

Conference	2008 International SoC Design Conference, ISOCC 2008
Country/Territory	Korea, Republic of
City	Busan
Period	24/11/08 → 25/11/08

Keywords

Embedded processor
Soft-core
System on chip(SoC)

Access to Document

10.1109/SOCDC.2008.4815746

Cite this

@inproceedings{c3a83151c7a144b09a93cdb988d16dbe,

title = "Design of high-performance 32-bit embedded processor",

abstract = "This paper describes the implementation of highperformance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS rocess and the real-time edge detection system is designed with Altera FPGA for evaluation system.",

keywords = "Embedded processor, Soft-core, System on chip(SoC)",

author = "Kim Ji-Hoon and You Duk-Hyun and Kwon Ki-Seok and Bae Eun-Joo and Son WonHee and Park In-Cheol",

year = "2008",

doi = "10.1109/SOCDC.2008.4815746",

language = "English",

isbn = "9781424425990",

series = "2008 International SoC Design Conference, ISOCC 2008",

pages = "III54--III55",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",

}

Ji-Hoon, K, Duk-Hyun, Y, Ki-Seok, K, Eun-Joo, B, WonHee, S & In-Cheol, P 2008, Design of high-performance 32-bit embedded processor. in 2008 International SoC Design Conference, ISOCC 2008., 4815746, 2008 International SoC Design Conference, ISOCC 2008, vol. 3, pp. III54-III55, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 24/11/08. https://doi.org/10.1109/SOCDC.2008.4815746

TY - GEN

T1 - Design of high-performance 32-bit embedded processor

AU - Ji-Hoon, Kim

AU - Duk-Hyun, You

AU - Ki-Seok, Kwon

AU - Eun-Joo, Bae

AU - WonHee, Son

AU - In-Cheol, Park

PY - 2008

Y1 - 2008

N2 - This paper describes the implementation of highperformance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS rocess and the real-time edge detection system is designed with Altera FPGA for evaluation system.

AB - This paper describes the implementation of highperformance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of Reduced Instruction Set Computer(RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18um 1P4M CMOS rocess and the real-time edge detection system is designed with Altera FPGA for evaluation system.

KW - Embedded processor

KW - Soft-core

KW - System on chip(SoC)

UR - http://www.scopus.com/inward/record.url?scp=67650675668&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2008.4815746

DO - 10.1109/SOCDC.2008.4815746

M3 - Conference contribution

AN - SCOPUS:67650675668

SN - 9781424425990

T3 - 2008 International SoC Design Conference, ISOCC 2008

SP - III54-III55

BT - 2008 International SoC Design Conference, ISOCC 2008

T2 - 2008 International SoC Design Conference, ISOCC 2008

Y2 - 24 November 2008 through 25 November 2008

ER -

Design of high-performance 32-bit embedded processor

Abstract

Publication series

Conference

Keywords

Access to Document

Fingerprint

Cite this