Design of a low noise amplifier employing on-chip notch filters for blocker rejection

This paper presents the design of a low noise amplifier (LNA) with on-chip notch filters for LTE cellular applications. The on-chip notch filters act as harmonic signal attenuators thereby notching out notorious blocker components that may occur at the harmonics of the local oscillator (LO) in the operation of direct conversion receiver. Proposed LNA consists of a cascode common-source (CS) amplifier with inductor degeneration as the input stage, cascaded with another cascode common-source stage as a second stage, and an output buffer for load impedance matching. Combining the degeneration inductor with an additional capacitor at the source gives an LC notch filter operation. The input impedance is therefore modulated along with the degenerated notch impedance at the fundamental and third harmonic frequencies of the LO. Similarly, the parasitic capacitance of the CS and common-gate (CG) are resonated with the intermediate inductor between the cascode CS and CG thereby providing blocker rejections at third and fifth harmonics of the LO. The proposed LNA was designed in TSMC 40 nm CMOS process with simulation results obtained as; S21 of 33 dB, noise figure (NF) of 1.58 dB at 1.5 GHz, and S11 well below -10 dB from 1.3 - 1.71 GHz as the operational bandwidth (LTE receive bands 11, 21, 24, 32 and 45). Additionally, blocker signals occurring at $3\omega_{o}$ and $5\omega_{o}$ of the LO were rejected by -83 dBc and -98 dBc respectively while consuming only 9 mA DC bias current from a 1.2 V supply.