Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters

Raymond Gyaang; Dong Ho Lee; Jusung Kim

doi:10.1109/ISOCC50952.2020.9332933

Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters

Raymond Gyaang, Dong Ho Lee, Jusung Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A low noise amplifier (LNA) with an on-chip dual notch filters for the rejection of blockers at the 3rd and 5th harmonic frequencies is presented in this work. A resistive feedback current-reuse (RFCR) architecture is utilized to provide broadband input impedance matching, low noise, and high linearity simultaneously. The proposed LNA has been designed using 40nm CMOS technology and verified from the post-layout simulations. With Band 8 (880MHz-915MHz) operating frequency range, the proposed LNA attained a maximum power gain (S21) of 23 dB, minimum noise figure (NF) of 3.7 dB. The 3rd and 5th harmonic rejections are 36.5 dBc and 45.5 dBc when injected with 0.9 GHz input frequency.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	31-32
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332933
State	Published - 21 Oct 2020
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 21 Oct 2020 → 24 Oct 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	21/10/20 → 24/10/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

dual notch filters
harmonic rejection LNA
resistive feedback current-reuse

Access to Document

10.1109/ISOCC50952.2020.9332933

Cite this

Gyaang, R., Lee, D. H., & Kim, J. (2020). Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 31-32). Article 9332933 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332933

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title = "Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters",

abstract = "A low noise amplifier (LNA) with an on-chip dual notch filters for the rejection of blockers at the 3rd and 5th harmonic frequencies is presented in this work. A resistive feedback current-reuse (RFCR) architecture is utilized to provide broadband input impedance matching, low noise, and high linearity simultaneously. The proposed LNA has been designed using 40nm CMOS technology and verified from the post-layout simulations. With Band 8 (880MHz-915MHz) operating frequency range, the proposed LNA attained a maximum power gain (S21) of 23 dB, minimum noise figure (NF) of 3.7 dB. The 3rd and 5th harmonic rejections are 36.5 dBc and 45.5 dBc when injected with 0.9 GHz input frequency.",

keywords = "dual notch filters, harmonic rejection LNA, resistive feedback current-reuse",

author = "Raymond Gyaang and Lee, \{Dong Ho\} and Jusung Kim",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

month = oct,

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doi = "10.1109/ISOCC50952.2020.9332933",

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Gyaang, R, Lee, DH & Kim, J 2020, Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332933, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 31-32, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 21/10/20. https://doi.org/10.1109/ISOCC50952.2020.9332933

Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters. / Gyaang, Raymond; Lee, Dong Ho; Kim, Jusung.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 31-32 9332933 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Gyaang, Raymond

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N2 - A low noise amplifier (LNA) with an on-chip dual notch filters for the rejection of blockers at the 3rd and 5th harmonic frequencies is presented in this work. A resistive feedback current-reuse (RFCR) architecture is utilized to provide broadband input impedance matching, low noise, and high linearity simultaneously. The proposed LNA has been designed using 40nm CMOS technology and verified from the post-layout simulations. With Band 8 (880MHz-915MHz) operating frequency range, the proposed LNA attained a maximum power gain (S21) of 23 dB, minimum noise figure (NF) of 3.7 dB. The 3rd and 5th harmonic rejections are 36.5 dBc and 45.5 dBc when injected with 0.9 GHz input frequency.

AB - A low noise amplifier (LNA) with an on-chip dual notch filters for the rejection of blockers at the 3rd and 5th harmonic frequencies is presented in this work. A resistive feedback current-reuse (RFCR) architecture is utilized to provide broadband input impedance matching, low noise, and high linearity simultaneously. The proposed LNA has been designed using 40nm CMOS technology and verified from the post-layout simulations. With Band 8 (880MHz-915MHz) operating frequency range, the proposed LNA attained a maximum power gain (S21) of 23 dB, minimum noise figure (NF) of 3.7 dB. The 3rd and 5th harmonic rejections are 36.5 dBc and 45.5 dBc when injected with 0.9 GHz input frequency.

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KW - resistive feedback current-reuse

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BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters

Abstract

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Keywords

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