Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

Seongjae Cho, Il Han Park, Tae Hun Kim, Jae Sung Sim, Ki Whan Song, Jong Duk Lee, Hyungcheol Shin, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND- and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si 3N 4 used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.

Original languageEnglish
Pages (from-to)180-184
Number of pages5
JournalIEEE Transactions on Nanotechnology
Issue number3
StatePublished - May 2006

Bibliographical note

Funding Information:
Manuscript received June 30, 2005; revised October 12, 2005. This work was supported by Samsung Electronics Corporation through the cooperative project “Research on Structure and Characterization of the Nonvolatile Memory Devices.” The review of this paper was arranged by Guest Editor M. Tabe.


  • Operating schemes
  • Read disturbance
  • Two-bit floating-gate-type nonvolative memory (NVM) cell


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