Design and Electrical Characterization of 2-T Thyristor RAM with Low Power Consumption

Youngmin Kim, Min Woo Kwon, Kyung Chang Ryoo, Seongjae Cho, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (Twrite) and erase time (Terase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 105. Also, Vwrite and erase voltage (Verase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

Original languageEnglish
Pages (from-to)355-358
Number of pages4
JournalIEEE Electron Device Letters
Issue number3
StatePublished - Mar 2018

Bibliographical note

Publisher Copyright:
© 2018 IEEE.


  • 2-T TRAM
  • TCAD
  • Thyristor
  • capacitorless DRAM
  • low power consumption
  • operation window


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