Design and Electrical Characterization of 2-T Thyristor RAM with Low Power Consumption

Youngmin Kim; Min Woo Kwon; Kyung Chang Ryoo; Seongjae Cho; Byung Gook Park

doi:10.1109/LED.2018.2796139

Design and Electrical Characterization of 2-T Thyristor RAM with Low Power Consumption

Youngmin Kim, Min Woo Kwon, Kyung Chang Ryoo, Seongjae Cho, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (T_write) and erase time (T_erase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 10⁵. Also, V_write and erase voltage (V_erase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

Original language	English
Pages (from-to)	355-358
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	39
Issue number	3
DOIs	https://doi.org/10.1109/LED.2018.2796139
State	Published - Mar 2018

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

2-T TRAM
TCAD
Thyristor
capacitorless DRAM
low power consumption
operation window

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/LED.2018.2796139

Cite this

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title = "Design and Electrical Characterization of 2-T Thyristor RAM with Low Power Consumption",

abstract = "In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (Twrite) and erase time (Terase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 105. Also, Vwrite and erase voltage (Verase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.",

keywords = "2-T TRAM, TCAD, Thyristor, capacitorless DRAM, low power consumption, operation window",

author = "Youngmin Kim and Kwon, {Min Woo} and Ryoo, {Kyung Chang} and Seongjae Cho and Park, {Byung Gook}",

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AU - Park, Byung Gook

PY - 2018/3

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N2 - In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (Twrite) and erase time (Terase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 105. Also, Vwrite and erase voltage (Verase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

AB - In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (Twrite) and erase time (Terase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 105. Also, Vwrite and erase voltage (Verase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

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KW - TCAD

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KW - operation window

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Design and Electrical Characterization of 2-T Thyristor RAM with Low Power Consumption

Abstract

Bibliographical note

Keywords

UN SDGs

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