Design and characterization of two-terminal thyristor dynamic random-access memory with a localized lightly-doped base insertion for improving data retention

Scaling challenges in dynamic random-access memory (DRAM) have driven the development of one-transistor capacitor-less (1T) DRAM architectures, such as Thyristor RAM (TRAM). However, silicon-based two-terminal TRAM (2-T TRAM) suffers from short retention times, limiting its practical application. This study proposes a localized lightly doped base (LLDB) structure to address this issue. By optimizing the LLDB doping concentration to 1.0 × 10¹⁷ cm⁻³, the retention time is improved by 138.49% to 601 ms, while energy consumption is reduced by 3.76% to 149.15 pJ. Simulation results confirm that the LLDB structure effectively suppresses Shockley-Read-Hall recombination, thereby enhancing retention characteristics and energy efficiency. These improvements make the LLDB-enhanced 2-T TRAM a promising candidate for high-performance, compact memory applications.