Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

Jae Hwa Seo, Young Jun Yoon, Seongmin Lee, Jung Hee Lee, Seongjae Cho, In Man Kang

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29 Scopus citations


In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III-V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (tepi) and height of source region (Hsource) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (Ion) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (Vt) of 0.1 V, current gain cut-off frequency (fT) of 12 GHz, and maximum oscillation frequency (fmax) of 283 GHz.

Original languageEnglish
Pages (from-to)208-212
Number of pages5
JournalCurrent Applied Physics
Issue number3
StatePublished - Mar 2015

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (No. 2013-011522 , 2012–0005671 ), and in part by Samsung Electronics Co. This work was also supported by Global Ph.D. Fellowship Program through the NRF funded by the MEST ( 2013H1A2A1034363 ).

Publisher Copyright:
© 2014 Elsevier B.V. All rights reserved.


  • Design optimization
  • Gate-all-around (GAA)
  • Low-power (LP)
  • Physical design
  • Tunneling field-effect transistor (TFET)


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