Abstract
In this work, a nanowire p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) coaxially having a Si core and a Ge peripheral channel is designed and characterized by device simulations. Owing to the high hole mobility of Ge, the device can be utilized for high-speed CMOS integrated circuits, with the effective confinement of mobile holes in Ge by the large valence band offset between Si and Ge. Source/drain doping concentrations and the ratio between the Si core and Ge channel thicknesses are determined. On the basis of the design results, the channel length is aggressively scaled down by evaluating the primary DC parameters in order to confirm device scalability and low-power applicability in sub-10-nm technology nodes.
| Original language | English |
|---|---|
| Article number | 114001 |
| Journal | Japanese Journal of Applied Physics |
| Volume | 55 |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 2016 |
Bibliographical note
Publisher Copyright:© 2016 The Japan Society of Applied Physics.
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