TY - GEN
T1 - Design and Analysis of Core-Gate Shell-Chanel 1T DRAM
AU - Ansari, Md Hasan Raza
AU - Yoon Lee, Jae
AU - Cho, Seongjae
AU - Park, Byung Gook
N1 - Funding Information:
ACKNOWLEDGEMENT This work was supported by the Ministry of Trade, Industry and Energy through KSRC support program (Grant No. 10080513).
Publisher Copyright:
© 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (Tret) of ~3.5 s at 85 °C for a gate length of 100 nm and ~5 ms at and 125 °C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write "1") and energy (0.02 fJ for read "0") consumptions for DRAM operations.
AB - The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (Tret) of ~3.5 s at 85 °C for a gate length of 100 nm and ~5 ms at and 125 °C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write "1") and energy (0.02 fJ for read "0") consumptions for DRAM operations.
UR - http://www.scopus.com/inward/record.url?scp=85092201531&partnerID=8YFLogxK
U2 - 10.1109/SNW50361.2020.9131619
DO - 10.1109/SNW50361.2020.9131619
M3 - Conference contribution
AN - SCOPUS:85092201531
T3 - 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
SP - 25
EP - 26
BT - 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Y2 - 13 June 2020 through 14 June 2020
ER -