Design and Analysis of Core-Gate Shell-Chanel 1T DRAM

Md Hasan Raza Ansari; Jae Yoon Lee; Seongjae Cho; Byung Gook Park

doi:10.1109/SNW50361.2020.9131619

Design and Analysis of Core-Gate Shell-Chanel 1T DRAM

Md Hasan Raza Ansari, Jae Yoon Lee, Seongjae Cho, Byung Gook Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (Tret) of ~3.5 s at 85 °C for a gate length of 100 nm and ~5 ms at and 125 °C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write "1") and energy (0.02 fJ for read "0") consumptions for DRAM operations.

Original language	English
Title of host publication	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	25-26
Number of pages	2
ISBN (Electronic)	9781728197357
DOIs	https://doi.org/10.1109/SNW50361.2020.9131619
State	Published - Jun 2020
Event	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States Duration: 13 Jun 2020 → 14 Jun 2020

Publication series

Name	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Country/Territory	United States
City	Honolulu
Period	13/06/20 → 14/06/20

Bibliographical note

Funding Information:
ACKNOWLEDGEMENT This work was supported by the Ministry of Trade, Industry and Energy through KSRC support program (Grant No. 10080513).

Publisher Copyright:
© 2020 IEEE.

Access to Document

10.1109/SNW50361.2020.9131619

Cite this

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title = "Design and Analysis of Core-Gate Shell-Chanel 1T DRAM",

abstract = "The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (Tret) of ~3.5 s at 85 °C for a gate length of 100 nm and ~5 ms at and 125 °C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write {"}1{"}) and energy (0.02 fJ for read {"}0{"}) consumptions for DRAM operations.",

author = "Ansari, {Md Hasan Raza} and {Yoon Lee}, Jae and Seongjae Cho and Park, {Byung Gook}",

note = "Funding Information: ACKNOWLEDGEMENT This work was supported by the Ministry of Trade, Industry and Energy through KSRC support program (Grant No. 10080513). Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 ; Conference date: 13-06-2020 Through 14-06-2020",

year = "2020",

month = jun,

doi = "10.1109/SNW50361.2020.9131619",

language = "English",

series = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Ansari, MHR, Yoon Lee, J, Cho, S & Park, BG 2020, Design and Analysis of Core-Gate Shell-Chanel 1T DRAM. in 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020., 9131619, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Institute of Electrical and Electronics Engineers Inc., pp. 25-26, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Honolulu, United States, 13/06/20. https://doi.org/10.1109/SNW50361.2020.9131619

Design and Analysis of Core-Gate Shell-Chanel 1T DRAM. / Ansari, Md Hasan Raza; Yoon Lee, Jae; Cho, Seongjae et al.
2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 25-26 9131619 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (Tret) of ~3.5 s at 85 °C for a gate length of 100 nm and ~5 ms at and 125 °C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write "1") and energy (0.02 fJ for read "0") consumptions for DRAM operations.

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Design and Analysis of Core-Gate Shell-Chanel 1T DRAM

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