Design and analysis of CMOS-compatible III-V compound electron-hole bilayer tunneling field-effect transistor for ultra-low-power applications

In this work, we design and analyze complementarymetal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p⁺ - p^- -n TFETs, which utilize BTBT across the source-to-channel junction.We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In_0.53Ga_0.47As EHB TFET show outstanding performance, with an on-state current (I_on) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (V_th) of 50 mV at V_DS =0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.