Depletion-enhanced body-isolation (DEBI) array on SOI for highly scalable and reliable NAND flash memories

Han Il Park; Tae Hun Kim; Seongjae Cho; Jung Hoon Lee; Jong Duk Lee; Byung Gook Park

doi:10.1109/TNANO.2006.869951

Depletion-enhanced body-isolation (DEBI) array on SOI for highly scalable and reliable NAND flash memories

Han Il Park, Tae Hun Kim, Seongjae Cho, Jung Hoon Lee, Jong Duk Lee, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

A novel array architecture [depletion-enhanced body-isolation (DEBI)] has been proposed for NAND-type flash memories, and its memory characteristics are investigated in detail by device simulations. Having the shallow junctions on the thin active area, the proposed array architecture achieves high device performances with a fully depleted silicon-on-insulator (FDSOI) structure and enables stable erase operation without any problems based on an SOI structure. In particular, during the program operation, the DEBI architecture exhibited excellent self-boost efficiency originating from the isolated body. This can reduce the program disturbance effectively and can lower the V _pass voltages.

Original language	English
Pages (from-to)	201-203
Number of pages	3
Journal	IEEE Transactions on Nanotechnology
Volume	5
Issue number	3
DOIs	https://doi.org/10.1109/TNANO.2006.869951
State	Published - May 2006

Bibliographical note

Funding Information:
Manuscript received June 30, 2005; revised November 28, 2005. This work was supported by the Tera-bit Level Nano Device Project. The review of this paper was arranged by Guest Editor M. Tabe. The authors are with the Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TNANO.2006.869951 Fig. 1. Proposed DEBI structure. (a) Plan view. (b) Cross-sectional view of A-A’. (c) Simulated array structure. Body bias can pass through the conducting path under the shallow N junction regions. L = 60 nm, T = 60 A; X = 350 A, and T = 600 A, respectively.

Keywords

Array
Depletion-enhanced body-isolation (DEBI)
Disturbance
Flash
NAND
Self-boost
Silicon-on-insulator (SOI)

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title = "Depletion-enhanced body-isolation (DEBI) array on SOI for highly scalable and reliable NAND flash memories",

abstract = "A novel array architecture [depletion-enhanced body-isolation (DEBI)] has been proposed for NAND-type flash memories, and its memory characteristics are investigated in detail by device simulations. Having the shallow junctions on the thin active area, the proposed array architecture achieves high device performances with a fully depleted silicon-on-insulator (FDSOI) structure and enables stable erase operation without any problems based on an SOI structure. In particular, during the program operation, the DEBI architecture exhibited excellent self-boost efficiency originating from the isolated body. This can reduce the program disturbance effectively and can lower the V pass voltages.",

keywords = "Array, Depletion-enhanced body-isolation (DEBI), Disturbance, Flash, NAND, Self-boost, Silicon-on-insulator (SOI)",

author = "Park, {Han Il} and Kim, {Tae Hun} and Seongjae Cho and Lee, {Jung Hoon} and Lee, {Jong Duk} and Park, {Byung Gook}",

note = "Funding Information: Manuscript received June 30, 2005; revised November 28, 2005. This work was supported by the Tera-bit Level Nano Device Project. The review of this paper was arranged by Guest Editor M. Tabe. The authors are with the Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TNANO.2006.869951 Fig. 1. Proposed DEBI structure. (a) Plan view. (b) Cross-sectional view of A-A{\textquoteright}. (c) Simulated array structure. Body bias can pass through the conducting path under the shallow N junction regions. L = 60 nm, T = 60 A; X = 350 A, and T = 600 A, respectively.",

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AU - Lee, Jong Duk

AU - Park, Byung Gook

N1 - Funding Information: Manuscript received June 30, 2005; revised November 28, 2005. This work was supported by the Tera-bit Level Nano Device Project. The review of this paper was arranged by Guest Editor M. Tabe. The authors are with the Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TNANO.2006.869951 Fig. 1. Proposed DEBI structure. (a) Plan view. (b) Cross-sectional view of A-A’. (c) Simulated array structure. Body bias can pass through the conducting path under the shallow N junction regions. L = 60 nm, T = 60 A; X = 350 A, and T = 600 A, respectively.

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AB - A novel array architecture [depletion-enhanced body-isolation (DEBI)] has been proposed for NAND-type flash memories, and its memory characteristics are investigated in detail by device simulations. Having the shallow junctions on the thin active area, the proposed array architecture achieves high device performances with a fully depleted silicon-on-insulator (FDSOI) structure and enables stable erase operation without any problems based on an SOI structure. In particular, during the program operation, the DEBI architecture exhibited excellent self-boost efficiency originating from the isolated body. This can reduce the program disturbance effectively and can lower the V pass voltages.

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Depletion-enhanced body-isolation (DEBI) array on SOI for highly scalable and reliable NAND flash memories

Abstract

Bibliographical note

Keywords

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