A novel array architecture [depletion-enhanced body-isolation (DEBI)] has been proposed for NAND-type flash memories, and its memory characteristics are investigated in detail by device simulations. Having the shallow junctions on the thin active area, the proposed array architecture achieves high device performances with a fully depleted silicon-on-insulator (FDSOI) structure and enables stable erase operation without any problems based on an SOI structure. In particular, during the program operation, the DEBI architecture exhibited excellent self-boost efficiency originating from the isolated body. This can reduce the program disturbance effectively and can lower the V pass voltages.
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Manuscript received June 30, 2005; revised November 28, 2005. This work was supported by the Tera-bit Level Nano Device Project. The review of this paper was arranged by Guest Editor M. Tabe. The authors are with the Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea (e-mail: firstname.lastname@example.org). Digital Object Identifier 10.1109/TNANO.2006.869951 Fig. 1. Proposed DEBI structure. (a) Plan view. (b) Cross-sectional view of A-A’. (c) Simulated array structure. Body bias can pass through the conducting path under the shallow N junction regions. L = 60 nm, T = 60 A; X = 350 A, and T = 600 A, respectively.
- Depletion-enhanced body-isolation (DEBI)
- Silicon-on-insulator (SOI)