Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

Eunjung Ko; Seon Haeng Lee; Md Hasan Raza Ansari; Seung Wook Ryu; Seongjae Cho

doi:10.35848/1882-0786/abb68f

Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

Eunjung Ko
, Seon Haeng Lee
, Md Hasan Raza Ansari
, Seung Wook Ryu
, Seongjae Cho

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The effects of precleaning processes by O₃ and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O₃ cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.

Original language	English
Article number	101003
Journal	Applied Physics Express
Volume	13
Issue number	10
DOIs	https://doi.org/10.35848/1882-0786/abb68f
State	Published - 1 Oct 2020

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© 2020 The Japan Society of Applied Physics

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@article{68561ec01be64b2a976bac99c80fbfce,

title = "Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods",

abstract = "The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.",

author = "Eunjung Ko and Lee, \{Seon Haeng\} and \{Raza Ansari\}, \{Md Hasan\} and Ryu, \{Seung Wook\} and Seongjae Cho",

note = "Publisher Copyright: {\textcopyright} 2020 The Japan Society of Applied Physics",

year = "2020",

month = oct,

day = "1",

doi = "10.35848/1882-0786/abb68f",

language = "English",

volume = "13",

journal = "Applied Physics Express",

issn = "1882-0778",

publisher = "Japan Society of Applied Physics",

number = "10",

}

TY - JOUR

T1 - Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

AU - Ko, Eunjung

AU - Lee, Seon Haeng

AU - Raza Ansari, Md Hasan

AU - Ryu, Seung Wook

AU - Cho, Seongjae

PY - 2020/10/1

Y1 - 2020/10/1

N2 - The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.

AB - The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.

UR - https://www.scopus.com/pages/publications/85092591465

U2 - 10.35848/1882-0786/abb68f

DO - 10.35848/1882-0786/abb68f

M3 - Article

AN - SCOPUS:85092591465

SN - 1882-0778

VL - 13

JO - Applied Physics Express

JF - Applied Physics Express

IS - 10

M1 - 101003

ER -

Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

Abstract

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