TY - JOUR
T1 - Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods
AU - Ko, Eunjung
AU - Lee, Seon Haeng
AU - Raza Ansari, Md Hasan
AU - Ryu, Seung Wook
AU - Cho, Seongjae
N1 - Publisher Copyright:
© 2020 The Japan Society of Applied Physics
PY - 2020/10/1
Y1 - 2020/10/1
N2 - The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.
AB - The effects of precleaning processes by O3 and SC-1 in depositing high-κ gate dielectric are closely investigated in experimental comparison study. The study is made in the p-type MOSFET on the 28 nm technology node in product. O3 cleaning demonstrated significant effects of increasing the effective oxide thickness in the inversion operation mode, reducing the gate leakage, and suppressing the standby leakage current. The electrical performances of PMOSFETs fabricated employing these two different precleaning methods were analyzed, and furthermore, device reliability was evaluated. The negative bias temperature instability lifetime showed 4-fold difference depending on cleaning method.
UR - http://www.scopus.com/inward/record.url?scp=85092591465&partnerID=8YFLogxK
U2 - 10.35848/1882-0786/abb68f
DO - 10.35848/1882-0786/abb68f
M3 - Article
AN - SCOPUS:85092591465
SN - 1882-0778
VL - 13
JO - Applied Physics Express
JF - Applied Physics Express
IS - 10
M1 - 101003
ER -