Abstract
This work demonstrates design and performances of core-shell dual-gate nanowire synaptic transistor with short/long term plasticity. The novel structure helps equip better capacitive coupling between dual gates through full depletion of carriers from the Si channel and construct deeper potential well for charge storage, which eventually increases the probability for short-term-to-long-term memory transition by reducing the recombination. The dual-gate operation effectively realizes the short-and the long-term potentiation in the proposed device for hardware-driven neuromorphic system.
Original language | English |
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Title of host publication | 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728181769 |
DOIs | |
State | Published - 8 Apr 2021 |
Event | 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 - Chengdu, China Duration: 8 Apr 2021 → 11 Apr 2021 |
Publication series
Name | 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 |
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Conference
Conference | 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 |
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Country/Territory | China |
City | Chengdu |
Period | 8/04/21 → 11/04/21 |
Bibliographical note
Funding Information:Acknowledgments This work was supported in part by Nano · Material Technology Development Program through the National Research Foundation (NRF) funded by the Ministry of Science and ICT (MSIT) under Grant NRF-2016M3A7B4910348, and in part by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by MSIT under Grant 2020-0-01294-001.
Publisher Copyright:
© 2021 IEEE.
Keywords
- core-shell dual-gate
- neuromorphic hardware
- short-term plasticity
- synaptic transistor