Core-shell dual-gate nanowire charge-trap memory for synaptic operations for neuromorphic applications

Md Hasan Raza Ansari; Udaya Mohanan Kannan; Seongjae Cho

doi:10.3390/nano11071773

Core-shell dual-gate nanowire charge-trap memory for synaptic operations for neuromorphic applications

Md Hasan Raza Ansari, Udaya Mohanan Kannan, Seongjae Cho

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depres-sion (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural net-work, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

Original language	English
Article number	1773
Journal	Nanomaterials
Volume	11
Issue number	7
DOIs	https://doi.org/10.3390/nano11071773
State	Published - Jul 2021

Bibliographical note

Funding Information:
Funding: This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (No. 2016M3A7B4910348, Nano ∙ Material Technology Development Program, 50%) and was partly supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-01294, Development of IoT based edge computing ultra-low power artificial intelligent processor, 50%).

Publisher Copyright:
© 2021 by the authors. Licensee MDPI, Basel, Switzerland.

Keywords

Band-to-band tunneling
Charge-trap synaptic transistor
Long-term potentiation (LTP)
Neural network
Neuromorphic system
Pattern recognition
Short-term potentiation (STP)

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title = "Core-shell dual-gate nanowire charge-trap memory for synaptic operations for neuromorphic applications",

abstract = "This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depres-sion (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural net-work, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.",

keywords = "Band-to-band tunneling, Charge-trap synaptic transistor, Long-term potentiation (LTP), Neural network, Neuromorphic system, Pattern recognition, Short-term potentiation (STP)",

author = "Ansari, {Md Hasan Raza} and Kannan, {Udaya Mohanan} and Seongjae Cho",

note = "Funding Information: Funding: This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (No. 2016M3A7B4910348, Nano ∙ Material Technology Development Program, 50%) and was partly supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-01294, Development of IoT based edge computing ultra-low power artificial intelligent processor, 50%). Publisher Copyright: {\textcopyright} 2021 by the authors. Licensee MDPI, Basel, Switzerland.",

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N2 - This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depres-sion (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural net-work, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

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Core-shell dual-gate nanowire charge-trap memory for synaptic operations for neuromorphic applications

Abstract

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Keywords

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