CMOS optical receiver chipset for Gigabit Ethernet applications

Sung Eun Kim; Seong Jun Song; Sung Min Park; Hoi Jun Yoo

CMOS optical receiver chipset for Gigabit Ethernet applications

Sung Eun Kim, Seong Jun Song, Sung Min Park, Hoi Jun Yoo

Electronic and Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700 MHz bandwidth for 1 pF photodiode capacitance, 80 dBΩ transimpedance gain, -17 dBm sensitivity for BER of 10^-12, and 27 mW power consumption. In our design, the post-amplifier is omitted due to the large voltage swing of the TIA and to the high sensitivity of the proposed CDR. The CDR takes a half-rate clock technique and thus removes the necessity of a 1:2 demultiplexer. It achieves 40 mV_pp sensitivity due to the high sensitivity phase detector. The RMS clock jitter and data jitter are measured to be 3.9 ps_rms and 20.2 ps_rms, respectively. Two chips dissipate 127 mW from a single 2.5 V supply.

Original language	English
Pages (from-to)	I29-I32
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
State	Published - 2003
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

Cite this

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title = "CMOS optical receiver chipset for Gigabit Ethernet applications",

abstract = "This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700 MHz bandwidth for 1 pF photodiode capacitance, 80 dBΩ transimpedance gain, -17 dBm sensitivity for BER of 10-12, and 27 mW power consumption. In our design, the post-amplifier is omitted due to the large voltage swing of the TIA and to the high sensitivity of the proposed CDR. The CDR takes a half-rate clock technique and thus removes the necessity of a 1:2 demultiplexer. It achieves 40 mVpp sensitivity due to the high sensitivity phase detector. The RMS clock jitter and data jitter are measured to be 3.9 psrms and 20.2 psrms, respectively. Two chips dissipate 127 mW from a single 2.5 V supply.",

author = "Kim, {Sung Eun} and Song, {Seong Jun} and Park, {Sung Min} and Yoo, {Hoi Jun}",

year = "2003",

language = "English",

volume = "1",

pages = "I29--I32",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

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TY - JOUR

T1 - CMOS optical receiver chipset for Gigabit Ethernet applications

AU - Kim, Sung Eun

AU - Song, Seong Jun

AU - Park, Sung Min

AU - Yoo, Hoi Jun

PY - 2003

Y1 - 2003

N2 - This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700 MHz bandwidth for 1 pF photodiode capacitance, 80 dBΩ transimpedance gain, -17 dBm sensitivity for BER of 10-12, and 27 mW power consumption. In our design, the post-amplifier is omitted due to the large voltage swing of the TIA and to the high sensitivity of the proposed CDR. The CDR takes a half-rate clock technique and thus removes the necessity of a 1:2 demultiplexer. It achieves 40 mVpp sensitivity due to the high sensitivity phase detector. The RMS clock jitter and data jitter are measured to be 3.9 psrms and 20.2 psrms, respectively. Two chips dissipate 127 mW from a single 2.5 V supply.

AB - This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for Gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700 MHz bandwidth for 1 pF photodiode capacitance, 80 dBΩ transimpedance gain, -17 dBm sensitivity for BER of 10-12, and 27 mW power consumption. In our design, the post-amplifier is omitted due to the large voltage swing of the TIA and to the high sensitivity of the proposed CDR. The CDR takes a half-rate clock technique and thus removes the necessity of a 1:2 demultiplexer. It achieves 40 mVpp sensitivity due to the high sensitivity phase detector. The RMS clock jitter and data jitter are measured to be 3.9 psrms and 20.2 psrms, respectively. Two chips dissipate 127 mW from a single 2.5 V supply.

UR - http://www.scopus.com/inward/record.url?scp=0038158254&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0038158254

SN - 0271-4310

VL - 1

SP - I29-I32

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

CMOS optical receiver chipset for Gigabit Ethernet applications

Abstract

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