Characterization and Optimization of Inverted-T FinFET under Nanoscale Dimensions

Eunseon Yu, Keun Heo, Seongjae Cho

Research output: Contribution to journalArticlepeer-review

37 Scopus citations

Abstract

In this paper, a p-type inverted-T FinFET (IT FinFET) has been optimally structured. Focus is made on analyzing the inferior characteristics reported from the previously fabricated IT FinFETs, and obtaining better performances through a novel structure. IT FinFET has a higher layout efficiency and can thus provide larger drain current (I D) under the same dimension as that of a silicon-on-insulator (SOI) FinFET by securing the extended channels of ultrathin body (UTB) on the field region. We closely observe the leverages of fin width ( W fin), UTB height (H UTB), and gate length ( L g) on the operation characteristics using a 3-D technology computer-aided design simulation with quantum-mechanical models. W fin below 10 nm is evaluated to be suitable for strong gate controllability. We first examine a critical H UTB, beyond which a higher drive current is not obtained even with a greater channel width than that of FinFET. When H UTB = 3 and 10 nm, IT FinFET yields 13.3% and 142% of saturation current improvement compared with SOI FinFET under the same footprint. At extremely scaled L g, although the immunity against short-channel effects is slightly weaker than that of SOI FinFET, optimally designed IT FinFET can produce a higher current and demonstrates shorter intrinsic delay times.

Original languageEnglish
Article number8396843
Pages (from-to)3521-3527
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume65
Issue number8
DOIs
StatePublished - Aug 2018

Bibliographical note

Funding Information:
Manuscript received February 27, 2018; revised April 18, 2018; accepted June 5, 2018. Date of publication June 26, 2018; date of current version July 23, 2018. This work was supported in part by the Ministry of Trade, Industry and Energy and Korea Semiconductor Research Consortium support program for the development of the future semiconductor devices under Grant 10052928 and Grant 10080513, in part by the Ministry of Science, ICT and Future Planning under Grant NRF-2017R1A2B2011570, and in part by the IDEC Program. The review of this paper was arranged by Editor M. M. Cahay. (Corresponding author: Seongjae Cho.) E. Yu is with the Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, South Korea.

Publisher Copyright:
© 2018 IEEE.

Keywords

  • 3-D technology computer-aided design (TCAD) simulation
  • high current drive
  • high performance (HP)
  • intrinsic gate delay
  • inverted-T FinFET (IT FinFET)
  • low power operation
  • short-channel effects (SCEs)
  • silicon-on-insulator (SOI) FinFET
  • wavy FinFET

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