TY - GEN
T1 - Challenges and implications of memory management systems under fast SCM storage
AU - Park, Yunjoo
AU - Cho, Kyungwoon
AU - Bahn, Hyokyung
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by the ICT R&D program of MSIP/IITP (2018-0-00549, Extremely Scalable Order-preserving Operating System for Manycore and Non-volatile Memory) and also by the Basic Science Research program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2019R1A2C1009275). Hyokyung Bahn is the corresponding author of this paper.
Funding Information:
This work was supported by the ICT R&D program of MSIP/IITP (2018-0-00549, Extremely Scalable Orderpreserving Operating System for Manycore and Non-volatile Memory) and also by the Basic Science Research program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2019R1A2C1009275). Hyokyung Bahn is the corresponding author of this paper.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - Recently, Storage-Class Memory (SCM) has advanced as a new memory/storage medium, and legacy memory subsystems optimized for DRAM-HDD architectures need to be redesigned. In this paper, we revisit the memory subsystems that use SCM as an underlying storage device and discuss the challenges and implications of such systems. Specifically, we analyze two memory layers influenced by fast storage devices: buffer cache and paging systems. In case of buffer cache, our analysis shows that caching of a file block gains only when the block from SCM storage is accessed at least twice after entering the cache. This is contrasting to the HDD case, in which only a single access in the cache also gains. In case of paging systems, we found out that a small page is effective in improving data access latency although it does not gain in terms of the page fault ratio. However, we further observed that a small page degrades the TLB miss ratio, which eventually deteriorates the address translation latency. Thus determining an appropriate page size is necessary by considering the trade-off between address translation and data access latency, under SCM storage. We anticipate that the result of this paper will be helpful in designing memory subsystems with ever faster SCM storage devices.
AB - Recently, Storage-Class Memory (SCM) has advanced as a new memory/storage medium, and legacy memory subsystems optimized for DRAM-HDD architectures need to be redesigned. In this paper, we revisit the memory subsystems that use SCM as an underlying storage device and discuss the challenges and implications of such systems. Specifically, we analyze two memory layers influenced by fast storage devices: buffer cache and paging systems. In case of buffer cache, our analysis shows that caching of a file block gains only when the block from SCM storage is accessed at least twice after entering the cache. This is contrasting to the HDD case, in which only a single access in the cache also gains. In case of paging systems, we found out that a small page is effective in improving data access latency although it does not gain in terms of the page fault ratio. However, we further observed that a small page degrades the TLB miss ratio, which eventually deteriorates the address translation latency. Thus determining an appropriate page size is necessary by considering the trade-off between address translation and data access latency, under SCM storage. We anticipate that the result of this paper will be helpful in designing memory subsystems with ever faster SCM storage devices.
KW - Buffer cache
KW - Memory management
KW - Page size
KW - Paging system
KW - SCM (Storage-Class Memory)
UR - http://www.scopus.com/inward/record.url?scp=85087079126&partnerID=8YFLogxK
U2 - 10.1109/ICISCE48695.2019.00046
DO - 10.1109/ICISCE48695.2019.00046
M3 - Conference contribution
AN - SCOPUS:85087079126
T3 - Proceedings - 2019 6th International Conference on Information Science and Control Engineering, ICISCE 2019
SP - 190
EP - 194
BT - Proceedings - 2019 6th International Conference on Information Science and Control Engineering, ICISCE 2019
A2 - Li, Shaozi
A2 - Cheng, Yun
A2 - Dai, Ying
A2 - Ma, Jianwei
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Information Science and Control Engineering, ICISCE 2019
Y2 - 20 December 2019 through 22 December 2019
ER -