TY - GEN
T1 - Buffer cache management for combined MLC and SLC flash memories using both volatile and nonvolatile RAMs
AU - Park, Junseok
AU - Bahn, Hyokyung
AU - Koh, Kern
PY - 2009
Y1 - 2009
N2 - This paper presents a new buffer cache management scheme called DABC-NV for mixed MLC and SLC flash memories as the secondary storage and both byte-accessible NVRAM and conventional volatile RAM as their buffer caches. DABC-NV has four salient features. First, it allocates buffer cache space to MLC and SLC flash memories based on their I/O costs and then dynamically adjusts the allocated size according to the evolution of workloads. Second, it separately exploits read and write histories of block references, and thus it estimates future references of each operation more precisely. Third, it guarantees the complete consistency of write I/Os since all dirty data are cached in nonvolatile buffer caches. Fourth, metadata lists are maintained separately from cached blocks. This allows more efficient management of volatile and nonvolatile buffer caches based on read and write histories, respectively. Trace-driven simulations show that DABC-NV improves the I/O performance of embedded systems significantly. Specifically, it reduces I/O time by 24% on average compared to the CLOCK-NV algorithm.
AB - This paper presents a new buffer cache management scheme called DABC-NV for mixed MLC and SLC flash memories as the secondary storage and both byte-accessible NVRAM and conventional volatile RAM as their buffer caches. DABC-NV has four salient features. First, it allocates buffer cache space to MLC and SLC flash memories based on their I/O costs and then dynamically adjusts the allocated size according to the evolution of workloads. Second, it separately exploits read and write histories of block references, and thus it estimates future references of each operation more precisely. Third, it guarantees the complete consistency of write I/Os since all dirty data are cached in nonvolatile buffer caches. Fourth, metadata lists are maintained separately from cached blocks. This allows more efficient management of volatile and nonvolatile buffer caches based on read and write histories, respectively. Trace-driven simulations show that DABC-NV improves the I/O performance of embedded systems significantly. Specifically, it reduces I/O time by 24% on average compared to the CLOCK-NV algorithm.
KW - Buffer caching
KW - MLC flash memory
KW - NAND flash memory
KW - NVRAM
KW - Replacement algorithm
UR - http://www.scopus.com/inward/record.url?scp=72349087443&partnerID=8YFLogxK
U2 - 10.1109/RTCSA.2009.32
DO - 10.1109/RTCSA.2009.32
M3 - Conference contribution
AN - SCOPUS:72349087443
SN - 9780769537870
T3 - Proceedings - 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009
SP - 228
EP - 235
BT - Proceedings - 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009
T2 - 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009
Y2 - 24 August 2009 through 26 August 2009
ER -