Abstract
Most of weights in deep learning models are small, thus they show high bit sparsity in MSBs. Based on this observation, we propose a bit-serial processing architecture (BS2) that exploits such bit sparsity to maximize computing efficiency. In this architecture, a bit feed front-end (BFFE) logic selects only effectual operands that will be fed into a bit-serial adder-tree. We also introduce an offline weight permutation algorithm to avoid conflicts in the BFFE. Evaluation results show that our design outperforms the previous bit-serial architecture in terms of performance and energy efficiency.
| Original language | English |
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| Title of host publication | Proceedings - International SoC Design Conference 2024, ISOCC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 356-357 |
| Number of pages | 2 |
| ISBN (Electronic) | 9798350377088 |
| DOIs | |
| State | Published - 2024 |
| Event | 21st International System-on-Chip Design Conference, ISOCC 2024 - Sapporo, Japan Duration: 19 Aug 2024 → 22 Aug 2024 |
Publication series
| Name | Proceedings - International SoC Design Conference 2024, ISOCC 2024 |
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Conference
| Conference | 21st International System-on-Chip Design Conference, ISOCC 2024 |
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| Country/Territory | Japan |
| City | Sapporo |
| Period | 19/08/24 → 22/08/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Bit Serial
- Bit Sparsity
- Deep Learning Acceleration
