Arch NAND flash memory array with improved virtual source/drain performance

Wandong Kim, Jung Hoon Lee, Jang Gn Yun, Seongjae Cho, Dong Hua Li, Yoon Kim, Doo Hyun Kim, Gil Sung Lee, Se Hwan Park, Won Bo Shim, Jong Ho Lee, Hyungcheol Shin, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


In this letter, a novel SONOS NAND Flash memory array featuring arch-shaped silicon fin and extended word lines (WL) is proposed to improve virtual source/drain (VSD) performance. The arch shape concentrates electric field, resulting in higher electron concentration at the VSD region and higher on -state cell current. In addition, the extended WL process improves the short-channel-effect (SCE) immunity and I-V characteristics. To verify these, an arch VSD NAND array device was fabricated and characterized. The integrated device shows very small SCE while obtaining high on-state cell current. Program and disturbance characteristics of the device are also confirmed.

Original languageEnglish
Article number5605222
Pages (from-to)1374-1376
Number of pages3
JournalIEEE Electron Device Letters
Issue number12
StatePublished - Dec 2010

Bibliographical note

Funding Information:
Manuscript received August 9, 2010; revised August 26, 2010; accepted August 30, 2010. Date of publication October 18, 2010; date of current version November 24, 2010. This work was supported in part by Samsung Electronics Corporation and in part by the Inter-University Semiconductor Research Center, Seoul National University. The review of this letter was arranged by Editor T. Wang.


  • Extended word line (WL)
  • Flash memory
  • field concentration effect
  • virtual source/drain (VSD)


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