Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode

Hyeonjeong Kim, In Man Kang, Seongjae Cho, Wookyung Sun, Hyungsoon Shin

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6 Scopus citations


Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable memory which allow for ultrahigh density. A single crystal silicon-based junctionless (JL) transistor is unsuitable for a 1T-DRAM cell because the transistor's body is too thin to have a storage region and its junction barrier is too low to store holes. In contrast, a JL transistor with a thin poly-Si body can be used as a 1T-DRAM cell because it uses a grain boundary as its charge storage region instead of a floating body. We carried out intensive simulations of JL transistors with poly-Si body and confirmed the possibility of using a JL structure as a poly-Si 1T-DRAM cell. In addition, we analyzed the memory mechanism and characteristics of this structure.

Original languageEnglish
Article number105007
JournalSemiconductor Science and Technology
Issue number10
StatePublished - 9 Sep 2019

Bibliographical note

Publisher Copyright:
© 2019 IOP Publishing Ltd.


  • capacitorless DRAM
  • grain boundary
  • junctionless (JL) transistor
  • poly-Si 1T-DRAM


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