Analysis of a lateral grain boundary for reducing performance variations in poly-Si 1T-DRAM

Songyi Yoo, Wookyung Sun, Hyungsoon Shin

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

Original languageEnglish
Article number952
Issue number11
StatePublished - Nov 2020

Bibliographical note

Funding Information:
Funding: This work was supported by the Ministry of Trade, Industry and Energy under Grant 10080513 and RP-Grant 2019 of Ewha Womans University. This research was also supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (No. 2019R1A2C1084063).

Publisher Copyright:
© 2020 by the authors. Licensee MDPI, Basel, Switzerland.


  • 1T-DRAM
  • Capacitorless one-transistor dynamic random-access memory
  • GB location
  • Grain boundary
  • Lateral grain boundary (GB)
  • Polysilicon


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