Abstract
This paper presents a hardware accelerator for YOLOX, the popular object detection convolutional neural network (CNN) model. It features a novel 1D systolic adder trees (SATs) to efficiently handle 1 1 or 3 3 convolution. The corresponding data feeding logic is designed to provide activations seamlessly to SAT. Evaluation results performed on Nangate 45nm process show that the proposed accelerator achieves higher area and energy efficiency compared to the previous YOLOX accelerator.
| Original language | English |
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| Title of host publication | Proceedings - International SoC Design Conference 2024, ISOCC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 179-180 |
| Number of pages | 2 |
| ISBN (Electronic) | 9798350377088 |
| DOIs | |
| State | Published - 2024 |
| Event | 21st International System-on-Chip Design Conference, ISOCC 2024 - Sapporo, Japan Duration: 19 Aug 2024 → 22 Aug 2024 |
Publication series
| Name | Proceedings - International SoC Design Conference 2024, ISOCC 2024 |
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Conference
| Conference | 21st International System-on-Chip Design Conference, ISOCC 2024 |
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| Country/Territory | Japan |
| City | Sapporo |
| Period | 19/08/24 → 22/08/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Hardware Accelerator
- Systolic Adder Tree
- YOLOX
