An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain–Computer Interface SoCs

Wooseok Byun, Minkyu Je, Ji Hoon Kim

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Recently, there is increasing demand for energy-efficient signal processing in wearable visual-stimuli-based brain-computer interface (V-BCI) devices. For the better accuracy and the reduced latency of the V-BCI system, the target identification (TI) algorithm that analyzes brain signals is being advanced, and the importance of an energy-efficient accelerating chip that processes various linear algebra operations constituting the TI algorithms is growing. In this paper, we propose a domain-specific reconfigurable array processor (RAP) with a dynamically reconfigurable and scalable array including 5-heterogeneous processing elements (PEs) for the energy-efficient acceleration of basic linear algebra subprograms (BLAS) and matrix decompositions. The system-on-chip (SoC), including the proposed RAP, was fabricated in 130-nm CMOS technology with an area of 16.87-mm2 and measured at 1.0 V 90 MHz. The RAP achieved an information transfer rate (ITR) of 139.9-bits/min and a TI accuracy of 95.4% on a fabricated chip through an optimized TI algorithm and scalable array processing. In addition, the RAP has 16.8<inline-formula> <tex-math notation="LaTeX">\(\times\)</tex-math> </inline-formula> higher TI energy efficiency than prior work and achieved an energy efficiency of 2144.2-bits/min/mW for information transfer processing rate with the proposed TI algorithm. The RAP supports a greater variety of linear algebra operations and data sizes with hardware reconfiguration than the prior accelerators.

Original languageEnglish
Pages (from-to)1-14
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
StateAccepted/In press - 2022

Bibliographical note

Publisher Copyright:
IEEE

Keywords

  • Arrays
  • Brain-computer interface (BCI)
  • Hardware
  • Linear algebra
  • Memory management
  • Parallel processing
  • Systolic arrays
  • Visualization
  • domain-specific architecture
  • heterogeneous PE
  • linear algebra accelerator
  • reconfigurable array processor

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