An efficient design of IPCR(image processing cache register) for wavelet transform

Won Kyu Ha; Sang Han Lee; Sang Bok Cho; Sung Min Park; Jong Hwa Lee

An efficient design of IPCR(image processing cache register) for wavelet transform

Won Kyu Ha, Sang Han Lee, Sang Bok Cho, Sung Min Park, Jong Hwa Lee

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

An efficient algorithm for integer wavelet transform is proposed to reduce the hardware complexity by using lifting-based scheme. We designed an IPCR (image processing cache register) in VHDL for the proposed algorithm. The architecture of wavelet transform is composed of image processor, IPCR, original frame store, and redundant frame store. For this work only the IPCR block was implemented in FPGA platform. The designed IPCR contains two chains and one window block. This architecture has been synthesized using Max+PLUSII. The estimated cells of the proposed IPCR are 64 logic cells, and the estimated operation frequency is 47.84 MHz. We compared the proposed architecture with S-wavelet transform, assuming an 8x8 block horizontal computation. Our proposed architecture needs only 92 logic cells including one IPCR and two adders comparing with 192 logic cells of S-wavelet transform necessary eight registers and adders.

Original language	English
Title of host publication	Proceedings - KORUS 2003
Subtitle of host publication	7th Korea-Russia International Symposium on Science and Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	335-339
Number of pages	5
ISBN (Electronic)	8978686184, 9788978686181
State	Published - 2003
Event	7th Korea-Russia International Symposium on Science and Technology, KORUS 2003 - Ulsan, Korea, Republic of Duration: 28 Jun 2003 → 6 Jul 2003

Publication series

Name	Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology
Volume	2

Conference

Conference	7th Korea-Russia International Symposium on Science and Technology, KORUS 2003
Country/Territory	Korea, Republic of
City	Ulsan
Period	28/06/03 → 6/07/03

Bibliographical note

Publisher Copyright:
© 2003 7th Korea-Russia Intl Sym on Science.

Keywords

Algorithm design and analysis
Computer architecture
Field programmable gate arrays
Frequency estimation
Hardware
Image processing
Logic
Process design
Registers
Wavelet transforms

Cite this

Ha, W. K., Lee, S. H., Cho, S. B., Park, S. M., & Lee, J. H. (2003). An efficient design of IPCR(image processing cache register) for wavelet transform. In Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology (pp. 335-339). Article 1222631 (Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology; Vol. 2). Institute of Electrical and Electronics Engineers Inc..

Ha, Won Kyu ; Lee, Sang Han ; Cho, Sang Bok et al. / An efficient design of IPCR(image processing cache register) for wavelet transform. Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 335-339 (Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology).

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title = "An efficient design of IPCR(image processing cache register) for wavelet transform",

abstract = "An efficient algorithm for integer wavelet transform is proposed to reduce the hardware complexity by using lifting-based scheme. We designed an IPCR (image processing cache register) in VHDL for the proposed algorithm. The architecture of wavelet transform is composed of image processor, IPCR, original frame store, and redundant frame store. For this work only the IPCR block was implemented in FPGA platform. The designed IPCR contains two chains and one window block. This architecture has been synthesized using Max+PLUSII. The estimated cells of the proposed IPCR are 64 logic cells, and the estimated operation frequency is 47.84 MHz. We compared the proposed architecture with S-wavelet transform, assuming an 8x8 block horizontal computation. Our proposed architecture needs only 92 logic cells including one IPCR and two adders comparing with 192 logic cells of S-wavelet transform necessary eight registers and adders.",

keywords = "Algorithm design and analysis, Computer architecture, Field programmable gate arrays, Frequency estimation, Hardware, Image processing, Logic, Process design, Registers, Wavelet transforms",

author = "Ha, {Won Kyu} and Lee, {Sang Han} and Cho, {Sang Bok} and Park, {Sung Min} and Lee, {Jong Hwa}",

note = "Publisher Copyright: {\textcopyright} 2003 7th Korea-Russia Intl Sym on Science.; 7th Korea-Russia International Symposium on Science and Technology, KORUS 2003 ; Conference date: 28-06-2003 Through 06-07-2003",

year = "2003",

language = "English",

series = "Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Ha, WK, Lee, SH, Cho, SB, Park, SM & Lee, JH 2003, An efficient design of IPCR(image processing cache register) for wavelet transform. in Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology., 1222631, Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 335-339, 7th Korea-Russia International Symposium on Science and Technology, KORUS 2003, Ulsan, Korea, Republic of, 28/06/03.

An efficient design of IPCR(image processing cache register) for wavelet transform. / Ha, Won Kyu; Lee, Sang Han; Cho, Sang Bok et al.
Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology. Institute of Electrical and Electronics Engineers Inc., 2003. p. 335-339 1222631 (Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ha, Won Kyu

AU - Lee, Sang Han

AU - Cho, Sang Bok

AU - Park, Sung Min

AU - Lee, Jong Hwa

PY - 2003

Y1 - 2003

N2 - An efficient algorithm for integer wavelet transform is proposed to reduce the hardware complexity by using lifting-based scheme. We designed an IPCR (image processing cache register) in VHDL for the proposed algorithm. The architecture of wavelet transform is composed of image processor, IPCR, original frame store, and redundant frame store. For this work only the IPCR block was implemented in FPGA platform. The designed IPCR contains two chains and one window block. This architecture has been synthesized using Max+PLUSII. The estimated cells of the proposed IPCR are 64 logic cells, and the estimated operation frequency is 47.84 MHz. We compared the proposed architecture with S-wavelet transform, assuming an 8x8 block horizontal computation. Our proposed architecture needs only 92 logic cells including one IPCR and two adders comparing with 192 logic cells of S-wavelet transform necessary eight registers and adders.

AB - An efficient algorithm for integer wavelet transform is proposed to reduce the hardware complexity by using lifting-based scheme. We designed an IPCR (image processing cache register) in VHDL for the proposed algorithm. The architecture of wavelet transform is composed of image processor, IPCR, original frame store, and redundant frame store. For this work only the IPCR block was implemented in FPGA platform. The designed IPCR contains two chains and one window block. This architecture has been synthesized using Max+PLUSII. The estimated cells of the proposed IPCR are 64 logic cells, and the estimated operation frequency is 47.84 MHz. We compared the proposed architecture with S-wavelet transform, assuming an 8x8 block horizontal computation. Our proposed architecture needs only 92 logic cells including one IPCR and two adders comparing with 192 logic cells of S-wavelet transform necessary eight registers and adders.

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KW - Computer architecture

KW - Field programmable gate arrays

KW - Frequency estimation

KW - Hardware

KW - Image processing

KW - Logic

KW - Process design

KW - Registers

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BT - Proceedings - KORUS 2003

PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

Ha WK, Lee SH, Cho SB, Park SM, Lee JH. An efficient design of IPCR(image processing cache register) for wavelet transform. In Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology. Institute of Electrical and Electronics Engineers Inc. 2003. p. 335-339. 1222631. (Proceedings - KORUS 2003: 7th Korea-Russia International Symposium on Science and Technology).

An efficient design of IPCR(image processing cache register) for wavelet transform

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Bibliographical note

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