An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs

Engineering

• Series Resistance 100%
• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Analytical Model 100%
• Induced Degradation 100%
• Gate Voltage 50%
• Channel Device 50%
• Gate Bias 50%
• Prior Model 50%
• Feature Size 50%
• Saturates 50%
• Lower Limit 50%
• Failure Time 50%
• Physical Model 50%

Material Science

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Hot Carrier 100%