An analytical model for hot-carrier-induced degradation of deep-submicron n-channel LDD MOSFETs

A universal behavior of hot-carrier-induced degradation of n-channel LDD MOSFETs has been modeled for the first time. This new physical model is based on simple derivation from current reduction behavior due to series resistance, in combination with an empirical relation of mobility degradation in n-accumulation layers. In LDD devices, because the degradation mainly comes from increased series resistance, accurate modeling for current degradation is very important in short channel devices. The current degradation vs stress time curves show a tendency to saturate at higher stress but they are universally proportional to weighted time. The mobility degradation in the n-accumulation region has a lower limit. Based on these insights, a simple analytical model is proposed for deep-submicron LDD devices, and it is verified for a wide range of gate voltages. Compared with prior models, this universal model can dramatically reduce the required stress time and more accurately estimate the failure time of LDD devices. Furthermore, this model provides a basis to explain the dependence of device degradation on gate bias and feature sizes of LDD.