NVRAM is being considered as an additional memory/storage component of future computer systems. This paper investigates how much performance gain can be obtained if we add NVRAM as the memory/storage component of computer systems. Specifically, we present a storage system accelerator that utilizes a small size of NVRAM cache. To do so, we formally define the NVRAM caching problem and analyze the storage access patterns that can be exploited in managing NVRAM cache. Our analysis shows that there are more than 40% of single-write data in storage I/Os due to periodic flushes triggered from the host side. Based on this observation, we show that acceleration of storage performance can be maximized by using NVRAM as a selective storage cache device. Empirical evaluation results show that our storage architecture with flush-aware NVRAM cache reduces the total I/O time by 26% on average and up to 62% compared to the case that does not use our scheme.
|Title of host publication||Proceedings - 2018 5th International Conference on Information Science and Control Engineering, ICISCE 2018|
|Editors||Yun Cheng, Shaozi Li, Ying Dai|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|State||Published - 14 Jan 2019|
|Event||5th International Conference on Information Science and Control Engineering, ICISCE 2018 - Zhengzhou, Henan, China|
Duration: 20 Jul 2018 → 22 Jul 2018
|Name||Proceedings - 2018 5th International Conference on Information Science and Control Engineering, ICISCE 2018|
|Conference||5th International Conference on Information Science and Control Engineering, ICISCE 2018|
|Period||20/07/18 → 22/07/18|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by the ICT R&D program of MSIP/IITP (2018-0-00549, Extremely Scalable Order-preserving Operating System for Manycore and Non-volatile Memory) and also by the Basic Science Research program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2016R1A2B4015750). Hyokyung Bahn is the corresponding author of this paper.
© 2018 IEEE.
- storage accelerator
- storage cache
- storage system