Abstract
In this work, we have investigated the effects of trap-mediated tunneling on program inhibition in the 3-D NAND flash memory. By a series of rigorous array-level TCAD simulations, it has been found that the self-boosted channel in the unselected bitline experiences a potential drop by direct inter-band tunneling, which can be significantly accelerated by trap-mediated tunneling. It is judged both types of tunneling events are inevitable and proper methods to lessen them need to be sought since the body biasing cannot be controlled and the bitline channel is made of poly-Si having abundant trap sites in the current 3-D NAND flash memory technology.
Original language | English |
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Title of host publication | 2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 87-88 |
Number of pages | 2 |
ISBN (Electronic) | 9798350391633 |
DOIs | |
State | Published - 2024 |
Event | 2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024 - Honolulu, United States Duration: 15 Jun 2024 → 16 Jun 2024 |
Publication series
Name | 2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024 |
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Conference
Conference | 2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024 |
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Country/Territory | United States |
City | Honolulu |
Period | 15/06/24 → 16/06/24 |
Bibliographical note
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