A wide-gain-range intermediate frequency integrated circuit for a superheterodyne receiver

A wide-gain-range Intermediate Frequency (IF) integrated circuit is designed and implemented for a superheterodyne receiver in standard 0.18 μm CMOS technology. It consists mainly of a programmable attenuator, a Variable Gain Amplifier (VGA), a downconverting mixer and a fixed gain amplifier. The π-type-network attenuator is chosen over a T-type network one in order for a compact layout. The common-gate-input VGA is used for a high operation frequency, a small phase shift and a wide gain range. The common-gate Gilbert-type mixer with a dynamic current injection technique and a capacitive cross-coupling technique is employed for proper gain, low noise and high linearity. Furthermore, a Phase-Locked Loop (PLL) is also integrated monolithically so as to generate the desired local clock signal for the mixer. Measurement results show that, from an area of 2.16 mm×1.46 mm and power consumption of 234 mW, the IF chip is able to operate properly with a gain range of 5 dB ~ 57 dB, output power of above 0dBm, and so on. In addition, the on-chip local clock with an operation frequency of 660 MHz and a phase noise of-119.34 dBc @1 MHz is achieved.