The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.
- Application specific processor architecture
- Discrete Cosine Transform
- Image compression
- Inverse Discrete Cosine Transform
- Serial-parallel processor
- Systolic array