A serial-parallel architecture for two-dimensional Discrete Cosine and Inverse Discrete Cosine Transforms

Hyesook Lim; Vincenzo Piuri; Earl E. Swartzlander

doi:10.1109/12.895848

A serial-parallel architecture for two-dimensional Discrete Cosine and Inverse Discrete Cosine Transforms

Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

34 Scopus citations

Abstract

The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.

Original language	English
Pages (from-to)	1297-1309
Number of pages	13
Journal	IEEE Transactions on Computers
Volume	49
Issue number	12
DOIs	https://doi.org/10.1109/12.895848
State	Published - 2000

Keywords

Application specific processor architecture
Discrete Cosine Transform
Image compression
Inverse Discrete Cosine Transform
Serial-parallel processor
Systolic array

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10.1109/12.895848

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A serial-parallel architecture for two-dimensional Discrete Cosine and Inverse Discrete Cosine Transforms

Abstract

Keywords

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